399 lines
17 KiB
C
399 lines
17 KiB
C
/**
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* Copyright (c) 2021 Raspberry Pi (Trading) Ltd.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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// =============================================================================
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// Register block : RTC
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// Version : 1
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// Bus type : apb
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// Description : Register block to control RTC
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// =============================================================================
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#ifndef HARDWARE_REGS_RTC_DEFINED
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#define HARDWARE_REGS_RTC_DEFINED
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// =============================================================================
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// Register : RTC_CLKDIV_M1
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// Description : Divider minus 1 for the 1 second counter. Safe to change the
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// value when RTC is not enabled.
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#define RTC_CLKDIV_M1_OFFSET 0x00000000
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#define RTC_CLKDIV_M1_BITS 0x0000ffff
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#define RTC_CLKDIV_M1_RESET 0x00000000
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#define RTC_CLKDIV_M1_MSB 15
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#define RTC_CLKDIV_M1_LSB 0
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#define RTC_CLKDIV_M1_ACCESS "RW"
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// =============================================================================
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// Register : RTC_SETUP_0
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// Description : RTC setup register 0
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#define RTC_SETUP_0_OFFSET 0x00000004
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#define RTC_SETUP_0_BITS 0x00ffff1f
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#define RTC_SETUP_0_RESET 0x00000000
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// -----------------------------------------------------------------------------
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// Field : RTC_SETUP_0_YEAR
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// Description : Year
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#define RTC_SETUP_0_YEAR_RESET 0x000
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#define RTC_SETUP_0_YEAR_BITS 0x00fff000
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#define RTC_SETUP_0_YEAR_MSB 23
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#define RTC_SETUP_0_YEAR_LSB 12
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#define RTC_SETUP_0_YEAR_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : RTC_SETUP_0_MONTH
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// Description : Month (1..12)
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#define RTC_SETUP_0_MONTH_RESET 0x0
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#define RTC_SETUP_0_MONTH_BITS 0x00000f00
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#define RTC_SETUP_0_MONTH_MSB 11
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#define RTC_SETUP_0_MONTH_LSB 8
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#define RTC_SETUP_0_MONTH_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : RTC_SETUP_0_DAY
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// Description : Day of the month (1..31)
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#define RTC_SETUP_0_DAY_RESET 0x00
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#define RTC_SETUP_0_DAY_BITS 0x0000001f
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#define RTC_SETUP_0_DAY_MSB 4
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#define RTC_SETUP_0_DAY_LSB 0
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#define RTC_SETUP_0_DAY_ACCESS "RW"
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// =============================================================================
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// Register : RTC_SETUP_1
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// Description : RTC setup register 1
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#define RTC_SETUP_1_OFFSET 0x00000008
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#define RTC_SETUP_1_BITS 0x071f3f3f
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#define RTC_SETUP_1_RESET 0x00000000
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// -----------------------------------------------------------------------------
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// Field : RTC_SETUP_1_DOTW
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// Description : Day of the week: 1-Monday...0-Sunday ISO 8601 mod 7
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#define RTC_SETUP_1_DOTW_RESET 0x0
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#define RTC_SETUP_1_DOTW_BITS 0x07000000
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#define RTC_SETUP_1_DOTW_MSB 26
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#define RTC_SETUP_1_DOTW_LSB 24
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#define RTC_SETUP_1_DOTW_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : RTC_SETUP_1_HOUR
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// Description : Hours
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#define RTC_SETUP_1_HOUR_RESET 0x00
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#define RTC_SETUP_1_HOUR_BITS 0x001f0000
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#define RTC_SETUP_1_HOUR_MSB 20
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#define RTC_SETUP_1_HOUR_LSB 16
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#define RTC_SETUP_1_HOUR_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : RTC_SETUP_1_MIN
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// Description : Minutes
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#define RTC_SETUP_1_MIN_RESET 0x00
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#define RTC_SETUP_1_MIN_BITS 0x00003f00
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#define RTC_SETUP_1_MIN_MSB 13
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#define RTC_SETUP_1_MIN_LSB 8
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#define RTC_SETUP_1_MIN_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : RTC_SETUP_1_SEC
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// Description : Seconds
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#define RTC_SETUP_1_SEC_RESET 0x00
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#define RTC_SETUP_1_SEC_BITS 0x0000003f
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#define RTC_SETUP_1_SEC_MSB 5
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#define RTC_SETUP_1_SEC_LSB 0
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#define RTC_SETUP_1_SEC_ACCESS "RW"
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// =============================================================================
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// Register : RTC_CTRL
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// Description : RTC Control and status
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#define RTC_CTRL_OFFSET 0x0000000c
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#define RTC_CTRL_BITS 0x00000113
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#define RTC_CTRL_RESET 0x00000000
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// -----------------------------------------------------------------------------
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// Field : RTC_CTRL_FORCE_NOTLEAPYEAR
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// Description : If set, leapyear is forced off.
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// Useful for years divisible by 100 but not by 400
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#define RTC_CTRL_FORCE_NOTLEAPYEAR_RESET 0x0
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#define RTC_CTRL_FORCE_NOTLEAPYEAR_BITS 0x00000100
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#define RTC_CTRL_FORCE_NOTLEAPYEAR_MSB 8
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#define RTC_CTRL_FORCE_NOTLEAPYEAR_LSB 8
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#define RTC_CTRL_FORCE_NOTLEAPYEAR_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : RTC_CTRL_LOAD
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// Description : Load RTC
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#define RTC_CTRL_LOAD_RESET 0x0
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#define RTC_CTRL_LOAD_BITS 0x00000010
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#define RTC_CTRL_LOAD_MSB 4
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#define RTC_CTRL_LOAD_LSB 4
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#define RTC_CTRL_LOAD_ACCESS "SC"
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// -----------------------------------------------------------------------------
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// Field : RTC_CTRL_RTC_ACTIVE
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// Description : RTC enabled (running)
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#define RTC_CTRL_RTC_ACTIVE_RESET "-"
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#define RTC_CTRL_RTC_ACTIVE_BITS 0x00000002
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#define RTC_CTRL_RTC_ACTIVE_MSB 1
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#define RTC_CTRL_RTC_ACTIVE_LSB 1
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#define RTC_CTRL_RTC_ACTIVE_ACCESS "RO"
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// -----------------------------------------------------------------------------
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// Field : RTC_CTRL_RTC_ENABLE
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// Description : Enable RTC
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#define RTC_CTRL_RTC_ENABLE_RESET 0x0
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#define RTC_CTRL_RTC_ENABLE_BITS 0x00000001
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#define RTC_CTRL_RTC_ENABLE_MSB 0
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#define RTC_CTRL_RTC_ENABLE_LSB 0
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#define RTC_CTRL_RTC_ENABLE_ACCESS "RW"
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// =============================================================================
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// Register : RTC_IRQ_SETUP_0
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// Description : Interrupt setup register 0
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#define RTC_IRQ_SETUP_0_OFFSET 0x00000010
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#define RTC_IRQ_SETUP_0_BITS 0x37ffff1f
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#define RTC_IRQ_SETUP_0_RESET 0x00000000
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// -----------------------------------------------------------------------------
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// Field : RTC_IRQ_SETUP_0_MATCH_ACTIVE
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// Description : None
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#define RTC_IRQ_SETUP_0_MATCH_ACTIVE_RESET "-"
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#define RTC_IRQ_SETUP_0_MATCH_ACTIVE_BITS 0x20000000
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#define RTC_IRQ_SETUP_0_MATCH_ACTIVE_MSB 29
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#define RTC_IRQ_SETUP_0_MATCH_ACTIVE_LSB 29
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#define RTC_IRQ_SETUP_0_MATCH_ACTIVE_ACCESS "RO"
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// -----------------------------------------------------------------------------
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// Field : RTC_IRQ_SETUP_0_MATCH_ENA
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// Description : Global match enable. Don't change any other value while this
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// one is enabled
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#define RTC_IRQ_SETUP_0_MATCH_ENA_RESET 0x0
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#define RTC_IRQ_SETUP_0_MATCH_ENA_BITS 0x10000000
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#define RTC_IRQ_SETUP_0_MATCH_ENA_MSB 28
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#define RTC_IRQ_SETUP_0_MATCH_ENA_LSB 28
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#define RTC_IRQ_SETUP_0_MATCH_ENA_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : RTC_IRQ_SETUP_0_YEAR_ENA
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// Description : Enable year matching
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#define RTC_IRQ_SETUP_0_YEAR_ENA_RESET 0x0
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#define RTC_IRQ_SETUP_0_YEAR_ENA_BITS 0x04000000
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#define RTC_IRQ_SETUP_0_YEAR_ENA_MSB 26
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#define RTC_IRQ_SETUP_0_YEAR_ENA_LSB 26
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#define RTC_IRQ_SETUP_0_YEAR_ENA_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : RTC_IRQ_SETUP_0_MONTH_ENA
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// Description : Enable month matching
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#define RTC_IRQ_SETUP_0_MONTH_ENA_RESET 0x0
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#define RTC_IRQ_SETUP_0_MONTH_ENA_BITS 0x02000000
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#define RTC_IRQ_SETUP_0_MONTH_ENA_MSB 25
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#define RTC_IRQ_SETUP_0_MONTH_ENA_LSB 25
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#define RTC_IRQ_SETUP_0_MONTH_ENA_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : RTC_IRQ_SETUP_0_DAY_ENA
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// Description : Enable day matching
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#define RTC_IRQ_SETUP_0_DAY_ENA_RESET 0x0
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#define RTC_IRQ_SETUP_0_DAY_ENA_BITS 0x01000000
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#define RTC_IRQ_SETUP_0_DAY_ENA_MSB 24
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#define RTC_IRQ_SETUP_0_DAY_ENA_LSB 24
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#define RTC_IRQ_SETUP_0_DAY_ENA_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : RTC_IRQ_SETUP_0_YEAR
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// Description : Year
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#define RTC_IRQ_SETUP_0_YEAR_RESET 0x000
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#define RTC_IRQ_SETUP_0_YEAR_BITS 0x00fff000
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#define RTC_IRQ_SETUP_0_YEAR_MSB 23
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#define RTC_IRQ_SETUP_0_YEAR_LSB 12
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#define RTC_IRQ_SETUP_0_YEAR_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : RTC_IRQ_SETUP_0_MONTH
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// Description : Month (1..12)
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#define RTC_IRQ_SETUP_0_MONTH_RESET 0x0
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#define RTC_IRQ_SETUP_0_MONTH_BITS 0x00000f00
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#define RTC_IRQ_SETUP_0_MONTH_MSB 11
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#define RTC_IRQ_SETUP_0_MONTH_LSB 8
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#define RTC_IRQ_SETUP_0_MONTH_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : RTC_IRQ_SETUP_0_DAY
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// Description : Day of the month (1..31)
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#define RTC_IRQ_SETUP_0_DAY_RESET 0x00
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#define RTC_IRQ_SETUP_0_DAY_BITS 0x0000001f
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#define RTC_IRQ_SETUP_0_DAY_MSB 4
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#define RTC_IRQ_SETUP_0_DAY_LSB 0
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#define RTC_IRQ_SETUP_0_DAY_ACCESS "RW"
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// =============================================================================
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// Register : RTC_IRQ_SETUP_1
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// Description : Interrupt setup register 1
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#define RTC_IRQ_SETUP_1_OFFSET 0x00000014
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#define RTC_IRQ_SETUP_1_BITS 0xf71f3f3f
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#define RTC_IRQ_SETUP_1_RESET 0x00000000
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// -----------------------------------------------------------------------------
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// Field : RTC_IRQ_SETUP_1_DOTW_ENA
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// Description : Enable day of the week matching
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#define RTC_IRQ_SETUP_1_DOTW_ENA_RESET 0x0
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#define RTC_IRQ_SETUP_1_DOTW_ENA_BITS 0x80000000
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#define RTC_IRQ_SETUP_1_DOTW_ENA_MSB 31
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#define RTC_IRQ_SETUP_1_DOTW_ENA_LSB 31
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#define RTC_IRQ_SETUP_1_DOTW_ENA_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : RTC_IRQ_SETUP_1_HOUR_ENA
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// Description : Enable hour matching
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#define RTC_IRQ_SETUP_1_HOUR_ENA_RESET 0x0
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#define RTC_IRQ_SETUP_1_HOUR_ENA_BITS 0x40000000
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#define RTC_IRQ_SETUP_1_HOUR_ENA_MSB 30
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#define RTC_IRQ_SETUP_1_HOUR_ENA_LSB 30
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#define RTC_IRQ_SETUP_1_HOUR_ENA_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : RTC_IRQ_SETUP_1_MIN_ENA
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// Description : Enable minute matching
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#define RTC_IRQ_SETUP_1_MIN_ENA_RESET 0x0
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#define RTC_IRQ_SETUP_1_MIN_ENA_BITS 0x20000000
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#define RTC_IRQ_SETUP_1_MIN_ENA_MSB 29
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#define RTC_IRQ_SETUP_1_MIN_ENA_LSB 29
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#define RTC_IRQ_SETUP_1_MIN_ENA_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : RTC_IRQ_SETUP_1_SEC_ENA
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// Description : Enable second matching
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#define RTC_IRQ_SETUP_1_SEC_ENA_RESET 0x0
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#define RTC_IRQ_SETUP_1_SEC_ENA_BITS 0x10000000
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#define RTC_IRQ_SETUP_1_SEC_ENA_MSB 28
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#define RTC_IRQ_SETUP_1_SEC_ENA_LSB 28
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#define RTC_IRQ_SETUP_1_SEC_ENA_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : RTC_IRQ_SETUP_1_DOTW
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// Description : Day of the week
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#define RTC_IRQ_SETUP_1_DOTW_RESET 0x0
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#define RTC_IRQ_SETUP_1_DOTW_BITS 0x07000000
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#define RTC_IRQ_SETUP_1_DOTW_MSB 26
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#define RTC_IRQ_SETUP_1_DOTW_LSB 24
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#define RTC_IRQ_SETUP_1_DOTW_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : RTC_IRQ_SETUP_1_HOUR
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// Description : Hours
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#define RTC_IRQ_SETUP_1_HOUR_RESET 0x00
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#define RTC_IRQ_SETUP_1_HOUR_BITS 0x001f0000
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#define RTC_IRQ_SETUP_1_HOUR_MSB 20
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#define RTC_IRQ_SETUP_1_HOUR_LSB 16
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#define RTC_IRQ_SETUP_1_HOUR_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : RTC_IRQ_SETUP_1_MIN
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// Description : Minutes
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#define RTC_IRQ_SETUP_1_MIN_RESET 0x00
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#define RTC_IRQ_SETUP_1_MIN_BITS 0x00003f00
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#define RTC_IRQ_SETUP_1_MIN_MSB 13
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#define RTC_IRQ_SETUP_1_MIN_LSB 8
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#define RTC_IRQ_SETUP_1_MIN_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : RTC_IRQ_SETUP_1_SEC
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// Description : Seconds
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#define RTC_IRQ_SETUP_1_SEC_RESET 0x00
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#define RTC_IRQ_SETUP_1_SEC_BITS 0x0000003f
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#define RTC_IRQ_SETUP_1_SEC_MSB 5
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#define RTC_IRQ_SETUP_1_SEC_LSB 0
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#define RTC_IRQ_SETUP_1_SEC_ACCESS "RW"
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// =============================================================================
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// Register : RTC_RTC_1
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// Description : RTC register 1.
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#define RTC_RTC_1_OFFSET 0x00000018
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#define RTC_RTC_1_BITS 0x00ffff1f
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#define RTC_RTC_1_RESET 0x00000000
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// -----------------------------------------------------------------------------
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// Field : RTC_RTC_1_YEAR
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// Description : Year
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#define RTC_RTC_1_YEAR_RESET "-"
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#define RTC_RTC_1_YEAR_BITS 0x00fff000
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#define RTC_RTC_1_YEAR_MSB 23
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#define RTC_RTC_1_YEAR_LSB 12
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#define RTC_RTC_1_YEAR_ACCESS "RO"
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// -----------------------------------------------------------------------------
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// Field : RTC_RTC_1_MONTH
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// Description : Month (1..12)
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#define RTC_RTC_1_MONTH_RESET "-"
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#define RTC_RTC_1_MONTH_BITS 0x00000f00
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#define RTC_RTC_1_MONTH_MSB 11
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#define RTC_RTC_1_MONTH_LSB 8
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#define RTC_RTC_1_MONTH_ACCESS "RO"
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// -----------------------------------------------------------------------------
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// Field : RTC_RTC_1_DAY
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// Description : Day of the month (1..31)
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#define RTC_RTC_1_DAY_RESET "-"
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#define RTC_RTC_1_DAY_BITS 0x0000001f
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#define RTC_RTC_1_DAY_MSB 4
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#define RTC_RTC_1_DAY_LSB 0
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#define RTC_RTC_1_DAY_ACCESS "RO"
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// =============================================================================
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// Register : RTC_RTC_0
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// Description : RTC register 0
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// Read this before RTC 1!
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#define RTC_RTC_0_OFFSET 0x0000001c
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#define RTC_RTC_0_BITS 0x071f3f3f
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#define RTC_RTC_0_RESET 0x00000000
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// -----------------------------------------------------------------------------
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// Field : RTC_RTC_0_DOTW
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// Description : Day of the week
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#define RTC_RTC_0_DOTW_RESET "-"
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#define RTC_RTC_0_DOTW_BITS 0x07000000
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#define RTC_RTC_0_DOTW_MSB 26
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#define RTC_RTC_0_DOTW_LSB 24
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#define RTC_RTC_0_DOTW_ACCESS "RF"
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// -----------------------------------------------------------------------------
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// Field : RTC_RTC_0_HOUR
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// Description : Hours
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#define RTC_RTC_0_HOUR_RESET "-"
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#define RTC_RTC_0_HOUR_BITS 0x001f0000
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#define RTC_RTC_0_HOUR_MSB 20
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#define RTC_RTC_0_HOUR_LSB 16
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#define RTC_RTC_0_HOUR_ACCESS "RF"
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// -----------------------------------------------------------------------------
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// Field : RTC_RTC_0_MIN
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// Description : Minutes
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#define RTC_RTC_0_MIN_RESET "-"
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#define RTC_RTC_0_MIN_BITS 0x00003f00
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#define RTC_RTC_0_MIN_MSB 13
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#define RTC_RTC_0_MIN_LSB 8
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#define RTC_RTC_0_MIN_ACCESS "RF"
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// -----------------------------------------------------------------------------
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// Field : RTC_RTC_0_SEC
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// Description : Seconds
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#define RTC_RTC_0_SEC_RESET "-"
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#define RTC_RTC_0_SEC_BITS 0x0000003f
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#define RTC_RTC_0_SEC_MSB 5
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#define RTC_RTC_0_SEC_LSB 0
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#define RTC_RTC_0_SEC_ACCESS "RF"
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// =============================================================================
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// Register : RTC_INTR
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// Description : Raw Interrupts
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#define RTC_INTR_OFFSET 0x00000020
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#define RTC_INTR_BITS 0x00000001
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#define RTC_INTR_RESET 0x00000000
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// -----------------------------------------------------------------------------
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// Field : RTC_INTR_RTC
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// Description : None
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#define RTC_INTR_RTC_RESET 0x0
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#define RTC_INTR_RTC_BITS 0x00000001
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#define RTC_INTR_RTC_MSB 0
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#define RTC_INTR_RTC_LSB 0
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#define RTC_INTR_RTC_ACCESS "RO"
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// =============================================================================
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// Register : RTC_INTE
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// Description : Interrupt Enable
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#define RTC_INTE_OFFSET 0x00000024
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#define RTC_INTE_BITS 0x00000001
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#define RTC_INTE_RESET 0x00000000
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// -----------------------------------------------------------------------------
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// Field : RTC_INTE_RTC
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// Description : None
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#define RTC_INTE_RTC_RESET 0x0
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#define RTC_INTE_RTC_BITS 0x00000001
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#define RTC_INTE_RTC_MSB 0
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#define RTC_INTE_RTC_LSB 0
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#define RTC_INTE_RTC_ACCESS "RW"
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// =============================================================================
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// Register : RTC_INTF
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// Description : Interrupt Force
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#define RTC_INTF_OFFSET 0x00000028
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#define RTC_INTF_BITS 0x00000001
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#define RTC_INTF_RESET 0x00000000
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// -----------------------------------------------------------------------------
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// Field : RTC_INTF_RTC
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// Description : None
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#define RTC_INTF_RTC_RESET 0x0
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#define RTC_INTF_RTC_BITS 0x00000001
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#define RTC_INTF_RTC_MSB 0
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#define RTC_INTF_RTC_LSB 0
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#define RTC_INTF_RTC_ACCESS "RW"
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// =============================================================================
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// Register : RTC_INTS
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// Description : Interrupt status after masking & forcing
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#define RTC_INTS_OFFSET 0x0000002c
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#define RTC_INTS_BITS 0x00000001
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#define RTC_INTS_RESET 0x00000000
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// -----------------------------------------------------------------------------
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// Field : RTC_INTS_RTC
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// Description : None
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#define RTC_INTS_RTC_RESET 0x0
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#define RTC_INTS_RTC_BITS 0x00000001
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#define RTC_INTS_RTC_MSB 0
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#define RTC_INTS_RTC_LSB 0
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#define RTC_INTS_RTC_ACCESS "RO"
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// =============================================================================
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#endif // HARDWARE_REGS_RTC_DEFINED
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