161 lines
7.6 KiB
C
161 lines
7.6 KiB
C
/**
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* Copyright (c) 2021 Raspberry Pi (Trading) Ltd.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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// =============================================================================
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// Register block : BUSCTRL
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// Version : 1
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// Bus type : apb
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// Description : Register block for busfabric control signals and performance
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// counters
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// =============================================================================
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#ifndef HARDWARE_REGS_BUSCTRL_DEFINED
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#define HARDWARE_REGS_BUSCTRL_DEFINED
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// =============================================================================
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// Register : BUSCTRL_BUS_PRIORITY
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// Description : Set the priority of each master for bus arbitration.
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#define BUSCTRL_BUS_PRIORITY_OFFSET 0x00000000
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#define BUSCTRL_BUS_PRIORITY_BITS 0x00001111
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#define BUSCTRL_BUS_PRIORITY_RESET 0x00000000
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// -----------------------------------------------------------------------------
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// Field : BUSCTRL_BUS_PRIORITY_DMA_W
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// Description : 0 - low priority, 1 - high priority
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#define BUSCTRL_BUS_PRIORITY_DMA_W_RESET 0x0
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#define BUSCTRL_BUS_PRIORITY_DMA_W_BITS 0x00001000
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#define BUSCTRL_BUS_PRIORITY_DMA_W_MSB 12
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#define BUSCTRL_BUS_PRIORITY_DMA_W_LSB 12
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#define BUSCTRL_BUS_PRIORITY_DMA_W_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : BUSCTRL_BUS_PRIORITY_DMA_R
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// Description : 0 - low priority, 1 - high priority
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#define BUSCTRL_BUS_PRIORITY_DMA_R_RESET 0x0
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#define BUSCTRL_BUS_PRIORITY_DMA_R_BITS 0x00000100
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#define BUSCTRL_BUS_PRIORITY_DMA_R_MSB 8
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#define BUSCTRL_BUS_PRIORITY_DMA_R_LSB 8
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#define BUSCTRL_BUS_PRIORITY_DMA_R_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : BUSCTRL_BUS_PRIORITY_PROC1
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// Description : 0 - low priority, 1 - high priority
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#define BUSCTRL_BUS_PRIORITY_PROC1_RESET 0x0
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#define BUSCTRL_BUS_PRIORITY_PROC1_BITS 0x00000010
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#define BUSCTRL_BUS_PRIORITY_PROC1_MSB 4
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#define BUSCTRL_BUS_PRIORITY_PROC1_LSB 4
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#define BUSCTRL_BUS_PRIORITY_PROC1_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : BUSCTRL_BUS_PRIORITY_PROC0
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// Description : 0 - low priority, 1 - high priority
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#define BUSCTRL_BUS_PRIORITY_PROC0_RESET 0x0
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#define BUSCTRL_BUS_PRIORITY_PROC0_BITS 0x00000001
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#define BUSCTRL_BUS_PRIORITY_PROC0_MSB 0
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#define BUSCTRL_BUS_PRIORITY_PROC0_LSB 0
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#define BUSCTRL_BUS_PRIORITY_PROC0_ACCESS "RW"
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// =============================================================================
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// Register : BUSCTRL_BUS_PRIORITY_ACK
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// Description : Bus priority acknowledge
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// Goes to 1 once all arbiters have registered the new global
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// priority levels.
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// Arbiters update their local priority when servicing a new
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// nonsequential access.
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// In normal circumstances this will happen almost immediately.
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#define BUSCTRL_BUS_PRIORITY_ACK_OFFSET 0x00000004
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#define BUSCTRL_BUS_PRIORITY_ACK_BITS 0x00000001
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#define BUSCTRL_BUS_PRIORITY_ACK_RESET 0x00000000
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#define BUSCTRL_BUS_PRIORITY_ACK_MSB 0
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#define BUSCTRL_BUS_PRIORITY_ACK_LSB 0
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#define BUSCTRL_BUS_PRIORITY_ACK_ACCESS "RO"
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// =============================================================================
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// Register : BUSCTRL_PERFCTR0
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// Description : Bus fabric performance counter 0
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// Busfabric saturating performance counter 0
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// Count some event signal from the busfabric arbiters.
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// Write any value to clear. Select an event to count using
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// PERFSEL0
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#define BUSCTRL_PERFCTR0_OFFSET 0x00000008
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#define BUSCTRL_PERFCTR0_BITS 0x00ffffff
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#define BUSCTRL_PERFCTR0_RESET 0x00000000
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#define BUSCTRL_PERFCTR0_MSB 23
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#define BUSCTRL_PERFCTR0_LSB 0
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#define BUSCTRL_PERFCTR0_ACCESS "WC"
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// =============================================================================
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// Register : BUSCTRL_PERFSEL0
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// Description : Bus fabric performance event select for PERFCTR0
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// Select a performance event for PERFCTR0
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#define BUSCTRL_PERFSEL0_OFFSET 0x0000000c
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#define BUSCTRL_PERFSEL0_BITS 0x0000001f
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#define BUSCTRL_PERFSEL0_RESET 0x0000001f
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#define BUSCTRL_PERFSEL0_MSB 4
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#define BUSCTRL_PERFSEL0_LSB 0
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#define BUSCTRL_PERFSEL0_ACCESS "RW"
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// =============================================================================
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// Register : BUSCTRL_PERFCTR1
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// Description : Bus fabric performance counter 1
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// Busfabric saturating performance counter 1
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// Count some event signal from the busfabric arbiters.
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// Write any value to clear. Select an event to count using
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// PERFSEL1
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#define BUSCTRL_PERFCTR1_OFFSET 0x00000010
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#define BUSCTRL_PERFCTR1_BITS 0x00ffffff
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#define BUSCTRL_PERFCTR1_RESET 0x00000000
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#define BUSCTRL_PERFCTR1_MSB 23
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#define BUSCTRL_PERFCTR1_LSB 0
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#define BUSCTRL_PERFCTR1_ACCESS "WC"
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// =============================================================================
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// Register : BUSCTRL_PERFSEL1
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// Description : Bus fabric performance event select for PERFCTR1
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// Select a performance event for PERFCTR1
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#define BUSCTRL_PERFSEL1_OFFSET 0x00000014
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#define BUSCTRL_PERFSEL1_BITS 0x0000001f
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#define BUSCTRL_PERFSEL1_RESET 0x0000001f
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#define BUSCTRL_PERFSEL1_MSB 4
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#define BUSCTRL_PERFSEL1_LSB 0
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#define BUSCTRL_PERFSEL1_ACCESS "RW"
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// =============================================================================
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// Register : BUSCTRL_PERFCTR2
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// Description : Bus fabric performance counter 2
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// Busfabric saturating performance counter 2
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// Count some event signal from the busfabric arbiters.
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// Write any value to clear. Select an event to count using
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// PERFSEL2
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#define BUSCTRL_PERFCTR2_OFFSET 0x00000018
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#define BUSCTRL_PERFCTR2_BITS 0x00ffffff
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#define BUSCTRL_PERFCTR2_RESET 0x00000000
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#define BUSCTRL_PERFCTR2_MSB 23
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#define BUSCTRL_PERFCTR2_LSB 0
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#define BUSCTRL_PERFCTR2_ACCESS "WC"
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// =============================================================================
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// Register : BUSCTRL_PERFSEL2
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// Description : Bus fabric performance event select for PERFCTR2
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// Select a performance event for PERFCTR2
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#define BUSCTRL_PERFSEL2_OFFSET 0x0000001c
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#define BUSCTRL_PERFSEL2_BITS 0x0000001f
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#define BUSCTRL_PERFSEL2_RESET 0x0000001f
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#define BUSCTRL_PERFSEL2_MSB 4
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#define BUSCTRL_PERFSEL2_LSB 0
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#define BUSCTRL_PERFSEL2_ACCESS "RW"
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// =============================================================================
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// Register : BUSCTRL_PERFCTR3
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// Description : Bus fabric performance counter 3
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// Busfabric saturating performance counter 3
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// Count some event signal from the busfabric arbiters.
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// Write any value to clear. Select an event to count using
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// PERFSEL3
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#define BUSCTRL_PERFCTR3_OFFSET 0x00000020
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#define BUSCTRL_PERFCTR3_BITS 0x00ffffff
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#define BUSCTRL_PERFCTR3_RESET 0x00000000
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#define BUSCTRL_PERFCTR3_MSB 23
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#define BUSCTRL_PERFCTR3_LSB 0
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#define BUSCTRL_PERFCTR3_ACCESS "WC"
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// =============================================================================
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// Register : BUSCTRL_PERFSEL3
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// Description : Bus fabric performance event select for PERFCTR3
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// Select a performance event for PERFCTR3
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#define BUSCTRL_PERFSEL3_OFFSET 0x00000024
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#define BUSCTRL_PERFSEL3_BITS 0x0000001f
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#define BUSCTRL_PERFSEL3_RESET 0x0000001f
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#define BUSCTRL_PERFSEL3_MSB 4
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#define BUSCTRL_PERFSEL3_LSB 0
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#define BUSCTRL_PERFSEL3_ACCESS "RW"
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// =============================================================================
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#endif // HARDWARE_REGS_BUSCTRL_DEFINED
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