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ARM: atmel: sama5d4_xplained: enable spl support

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Signed-off-by: Bo Shen <voice.shen@atmel.com>
This commit is contained in:
Bo Shen
2014-12-15 13:24:39 +08:00
committed by Andreas Bießmann
parent 5a4c9c2287
commit 0b2a982420
6 changed files with 145 additions and 0 deletions
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85
board/atmel/sama5d4_xplained/sama5d4_xplained.c
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@@ -10,6 +10,7 @@
#include <asm/arch/at91_common.h>
#include <asm/arch/at91_pmc.h>
#include <asm/arch/at91_rstc.h>
#include <asm/arch/atmel_mpddrc.h>
#include <asm/arch/atmel_usba_udc.h>
#include <asm/arch/gpio.h>
#include <asm/arch/clk.h>
@@ -326,3 +327,87 @@ int board_eth_init(bd_t *bis)
return rc;
}
/* SPL */
#ifdef CONFIG_SPL_BUILD
void spl_board_init(void)
{
#ifdef CONFIG_SYS_USE_MMC
sama5d4_xplained_mci1_hw_init();
#elif CONFIG_SYS_USE_NANDFLASH
sama5d4_xplained_nand_hw_init();
#elif CONFIG_SYS_USE_SERIALFLASH
sama5d4_xplained_spi0_hw_init();
#endif
}
static void ddr2_conf(struct atmel_mpddr *ddr2)
{
ddr2->md = (ATMEL_MPDDRC_MD_DBW_32_BITS | ATMEL_MPDDRC_MD_DDR2_SDRAM);
ddr2->cr = (ATMEL_MPDDRC_CR_NC_COL_10 |
ATMEL_MPDDRC_CR_NR_ROW_14 |
ATMEL_MPDDRC_CR_CAS_DDR_CAS3 |
ATMEL_MPDDRC_CR_NB_8BANKS |
ATMEL_MPDDRC_CR_NDQS_DISABLED |
ATMEL_MPDDRC_CR_DECOD_INTERLEAVED |
ATMEL_MPDDRC_CR_UNAL_SUPPORTED);
ddr2->rtr = 0x2b0;
ddr2->tpr0 = (8 << ATMEL_MPDDRC_TPR0_TRAS_OFFSET |
3 << ATMEL_MPDDRC_TPR0_TRCD_OFFSET |
3 << ATMEL_MPDDRC_TPR0_TWR_OFFSET |
10 << ATMEL_MPDDRC_TPR0_TRC_OFFSET |
3 << ATMEL_MPDDRC_TPR0_TRP_OFFSET |
2 << ATMEL_MPDDRC_TPR0_TRRD_OFFSET |
2 << ATMEL_MPDDRC_TPR0_TWTR_OFFSET |
2 << ATMEL_MPDDRC_TPR0_TMRD_OFFSET);
ddr2->tpr1 = (2 << ATMEL_MPDDRC_TPR1_TXP_OFFSET |
200 << ATMEL_MPDDRC_TPR1_TXSRD_OFFSET |
25 << ATMEL_MPDDRC_TPR1_TXSNR_OFFSET |
23 << ATMEL_MPDDRC_TPR1_TRFC_OFFSET);
ddr2->tpr2 = (7 << ATMEL_MPDDRC_TPR2_TFAW_OFFSET |
2 << ATMEL_MPDDRC_TPR2_TRTP_OFFSET |
3 << ATMEL_MPDDRC_TPR2_TRPA_OFFSET |
2 << ATMEL_MPDDRC_TPR2_TXARDS_OFFSET |
8 << ATMEL_MPDDRC_TPR2_TXARD_OFFSET);
}
void mem_init(void)
{
struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
struct atmel_mpddr ddr2;
ddr2_conf(&ddr2);
/* enable MPDDR clock */
at91_periph_clk_enable(ATMEL_ID_MPDDRC);
writel(0x4, &pmc->scer);
/* DDRAM2 Controller initialize */
ddr2_init(ATMEL_BASE_DDRCS, &ddr2);
}
void at91_pmc_init(void)
{
struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
u32 tmp;
tmp = AT91_PMC_PLLAR_29 |
AT91_PMC_PLLXR_PLLCOUNT(0x3f) |
AT91_PMC_PLLXR_MUL(87) |
AT91_PMC_PLLXR_DIV(1);
at91_plla_init(tmp);
writel(0x0 << 8, &pmc->pllicpr);
tmp = AT91_PMC_MCKR_H32MXDIV |
AT91_PMC_MCKR_PLLADIV_2 |
AT91_PMC_MCKR_MDIV_3 |
AT91_PMC_MCKR_CSS_PLLA;
at91_mck_init(tmp);
}
#endif