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arc: select cache settings via menuconfig

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This change allows to keep board description clean and minimalistic.
This is especially helpful if one board may house different CPUs with
different features.

It is applicable to both FPGA-based boards or those that have CPUs
mounted on interchnagable daughter-boards.

Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
This commit is contained in:
Alexey Brodkin
2015-02-03 13:58:13 +03:00
parent 5ff40f3d42
commit 205e7a7b77
9 changed files with 30 additions and 17 deletions
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1
include/configs/arcangel4-be.h
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@@ -11,7 +11,6 @@
* CPU configuration
*/
#define CONFIG_SYS_BIG_ENDIAN
#define CONFIG_SYS_CACHELINE_SIZE 64
#define CONFIG_SYS_TIMER_RATE CONFIG_SYS_CLK_FREQ
/*

1
include/configs/arcangel4.h
View File

@@ -10,7 +10,6 @@
/*
* CPU configuration
*/
#define CONFIG_SYS_CACHELINE_SIZE 64
#define CONFIG_SYS_TIMER_RATE CONFIG_SYS_CLK_FREQ
/*

4
include/configs/axs101.h
View File

@@ -10,12 +10,8 @@
/*
* CPU configuration
*/
#define CONFIG_SYS_CACHELINE_SIZE 32
#define CONFIG_SYS_TIMER_RATE CONFIG_SYS_CLK_FREQ
/* NAND controller DMA doesn't work correctly with D$ enabled */
#define CONFIG_SYS_DCACHE_OFF
/*
* Board configuration
*/

1
include/configs/tb100.h
View File

@@ -12,7 +12,6 @@
/*
* CPU configuration
*/
#define CONFIG_SYS_CACHELINE_SIZE 32
#define CONFIG_SYS_TIMER_RATE CONFIG_SYS_CLK_FREQ
/*