MPC85xx: Add MPC8569 CPU support
There is a workaround for MPC8569 CPU Errata, which needs to set Bit 13 of LBCR in 4K bootpage. We setup a temp TLB for eLBC controller in bootpage, then invalidate it after LBCR bit 13 is set. Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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@@ -1609,8 +1609,19 @@ typedef struct ccsr_gur {
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char res2[12];
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uint gpiocr; /* 0xe0030 - GPIO control register */
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char res3[12];
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#if defined(CONFIG_MPC8569)
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uint plppar1;
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/* 0xe0040 - Platform port pin assignment register 1 */
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uint plppar2;
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/* 0xe0044 - Platform port pin assignment register 2 */
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uint plpdir1;
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/* 0xe0048 - Platform port pin direction register 1 */
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uint plpdir2;
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/* 0xe004c - Platform port pin direction register 2 */
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#else
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uint gpoutdr; /* 0xe0040 - General-purpose output data register */
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char res4[12];
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#endif
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uint gpindr; /* 0xe0050 - General-purpose input data register */
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char res5[12];
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uint pmuxcr; /* 0xe0060 - Alternate function signal multiplex control */
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@@ -1651,7 +1662,7 @@ typedef struct ccsr_gur {
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uint svr; /* 0xe00a4 - System version register */
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char res10a[8];
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uint rstcr; /* 0xe00b0 - Reset control register */
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#ifdef CONFIG_MPC8568
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#if defined(CONFIG_MPC8568)||defined(CONFIG_MPC8569)
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char res10b[76];
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par_io_t qe_par_io[7]; /* 0xe0100 - 0xe01bf */
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char res10c[3136];
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@@ -20,7 +20,9 @@
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typedef struct qe_iram {
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u32 iadd; /* I-RAM Address Register */
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u32 idata; /* I-RAM Data Register */
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u8 res0[0x78];
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u8 res0[0x4];
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u32 iready;
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u8 res1[0x70];
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} __attribute__ ((packed)) qe_iram_t;
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/* QE Interrupt Controller
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@@ -580,7 +582,7 @@ typedef struct qe_immap {
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u8 res14[0x300];
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u8 res15[0x3A00];
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u8 res16[0x8000]; /* 0x108000 - 0x110000 */
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#if defined(CONFIG_MPC8568)
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#if defined(CONFIG_MPC8568)||defined(CONFIG_MPC8569)
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u8 muram[0x10000]; /* 0x1_0000 - 0x2_0000 Multi-user RAM */
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u8 res17[0x20000]; /* 0x2_0000 - 0x4_0000 */
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#else
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@@ -592,7 +594,7 @@ typedef struct qe_immap {
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extern qe_map_t *qe_immr;
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#if defined(CONFIG_MPC8568)
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#if defined(CONFIG_MPC8568) || defined(CONFIG_MPC8569)
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#define QE_MURAM_SIZE 0x10000UL
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#elif defined(CONFIG_MPC8360)
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#define QE_MURAM_SIZE 0xc000UL
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@@ -955,6 +955,8 @@
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#define SVR_8567_E 0x807E00
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#define SVR_8568 0x807500
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#define SVR_8568_E 0x807D00
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#define SVR_8569 0x808000
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#define SVR_8569_E 0x808800
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#define SVR_8572 0x80E000
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#define SVR_8572_E 0x80E800
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#define SVR_P2020 0x80E200
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