MPC85xx: Add MPC8569 CPU support

There is a workaround for MPC8569 CPU Errata, which needs to set Bit 13 of
LBCR in 4K bootpage. We setup a temp TLB for eLBC controller in bootpage,
then invalidate it after LBCR bit 13 is set.

Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
This commit is contained in:
Haiying Wang
2009-03-27 17:02:44 -04:00
committed by Kumar Gala
parent 2d4de6ae5b
commit 22b6dbc169
7 changed files with 72 additions and 5 deletions

View File

@@ -1609,8 +1609,19 @@ typedef struct ccsr_gur {
char res2[12];
uint gpiocr; /* 0xe0030 - GPIO control register */
char res3[12];
#if defined(CONFIG_MPC8569)
uint plppar1;
/* 0xe0040 - Platform port pin assignment register 1 */
uint plppar2;
/* 0xe0044 - Platform port pin assignment register 2 */
uint plpdir1;
/* 0xe0048 - Platform port pin direction register 1 */
uint plpdir2;
/* 0xe004c - Platform port pin direction register 2 */
#else
uint gpoutdr; /* 0xe0040 - General-purpose output data register */
char res4[12];
#endif
uint gpindr; /* 0xe0050 - General-purpose input data register */
char res5[12];
uint pmuxcr; /* 0xe0060 - Alternate function signal multiplex control */
@@ -1651,7 +1662,7 @@ typedef struct ccsr_gur {
uint svr; /* 0xe00a4 - System version register */
char res10a[8];
uint rstcr; /* 0xe00b0 - Reset control register */
#ifdef CONFIG_MPC8568
#if defined(CONFIG_MPC8568)||defined(CONFIG_MPC8569)
char res10b[76];
par_io_t qe_par_io[7]; /* 0xe0100 - 0xe01bf */
char res10c[3136];

View File

@@ -20,7 +20,9 @@
typedef struct qe_iram {
u32 iadd; /* I-RAM Address Register */
u32 idata; /* I-RAM Data Register */
u8 res0[0x78];
u8 res0[0x4];
u32 iready;
u8 res1[0x70];
} __attribute__ ((packed)) qe_iram_t;
/* QE Interrupt Controller
@@ -580,7 +582,7 @@ typedef struct qe_immap {
u8 res14[0x300];
u8 res15[0x3A00];
u8 res16[0x8000]; /* 0x108000 - 0x110000 */
#if defined(CONFIG_MPC8568)
#if defined(CONFIG_MPC8568)||defined(CONFIG_MPC8569)
u8 muram[0x10000]; /* 0x1_0000 - 0x2_0000 Multi-user RAM */
u8 res17[0x20000]; /* 0x2_0000 - 0x4_0000 */
#else
@@ -592,7 +594,7 @@ typedef struct qe_immap {
extern qe_map_t *qe_immr;
#if defined(CONFIG_MPC8568)
#if defined(CONFIG_MPC8568) || defined(CONFIG_MPC8569)
#define QE_MURAM_SIZE 0x10000UL
#elif defined(CONFIG_MPC8360)
#define QE_MURAM_SIZE 0xc000UL

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@@ -955,6 +955,8 @@
#define SVR_8567_E 0x807E00
#define SVR_8568 0x807500
#define SVR_8568_E 0x807D00
#define SVR_8569 0x808000
#define SVR_8569_E 0x808800
#define SVR_8572 0x80E000
#define SVR_8572_E 0x80E800
#define SVR_P2020 0x80E200