Merge branch 'master' of git://git.denx.de/u-boot-ppc4xx
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@@ -117,6 +117,7 @@
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#define SDRAM_MCSTS_MRSC 0x80000000
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#define SDRAM_MCSTS_SRMS 0x40000000
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#define SDRAM_MCSTS_CIS 0x20000000
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#define SDRAM_MCSTS_IDLE_NOT 0x00000000 /* Mem contr not idle */
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/*
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* SDRAM Refresh Timer Register
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@@ -416,8 +417,7 @@
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#define SDRAM_SDTR3 0x87 /* DDR SDRAM timing 3 */
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#define SDRAM_MMODE 0x88 /* memory mode */
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#define SDRAM_MEMODE 0x89 /* memory extended mode */
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#define SDRAM_ECCCR 0x98 /* ECC error status */
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#define SDRAM_ECCES SDRAM_ECCCR
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#define SDRAM_ECCES 0x98 /* ECC error status */
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#define SDRAM_CID 0xA4 /* core ID */
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#ifndef CONFIG_405EX
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#define SDRAM_RID 0xA8 /* revision ID */
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@@ -1397,7 +1397,6 @@
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/*
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* Prototypes
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*/
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void inline blank_string(int size);
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inline void ppc4xx_ibm_ddr2_register_dump(void);
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u32 mfdcr_any(u32);
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void mtdcr_any(u32, u32);
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@@ -1405,6 +1404,8 @@ u32 ddr_wrdtr(u32);
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u32 ddr_clktr(u32);
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void spd_ddr_init_hang(void);
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u32 DQS_autocalibration(void);
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phys_size_t sdram_memsize(void);
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void dcbz_area(u32 start_address, u32 num_bytes);
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#endif /* __ASSEMBLY__ */
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#endif /* _PPC4xx_SDRAM_H_ */
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@@ -215,7 +215,6 @@
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/*-----------------------------------------------------------------------
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* DDR SDRAM
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*----------------------------------------------------------------------*/
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#define CONFIG_SYS_MBYTES_SDRAM (256) /* 256MB */
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#if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
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#define CONFIG_DDR_DATA_EYE /* use DDR2 optimization */
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#endif
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