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Merge branch 'master' of git://www.denx.de/git/u-boot-socfpga

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This commit is contained in:
Tom Rini
2015-12-19 22:05:31 -05:00
parent 1c0e84ca82 48275c96ff
commit 34059d8f50
35 changed files with 289 additions and 553 deletions
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15
include/configs/socfpga_arria5_socdk.h
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@@ -47,30 +47,15 @@
/* Ethernet on SoC (EMAC) */
#if defined(CONFIG_CMD_NET)
/* PHY */
#define CONFIG_PHY_MICREL
#define CONFIG_PHY_MICREL_KSZ9021
#define CONFIG_KSZ9021_CLK_SKEW_ENV "micrel-ksz9021-clk-skew"
#define CONFIG_KSZ9021_CLK_SKEW_VAL 0xf0f0
#define CONFIG_KSZ9021_DATA_SKEW_ENV "micrel-ksz9021-data-skew"
#define CONFIG_KSZ9021_DATA_SKEW_VAL 0x0
#endif
#define CONFIG_ENV_IS_IN_MMC
#define CONFIG_SYS_MMC_ENV_DEV 0 /* device 0 */
#define CONFIG_ENV_OFFSET 512 /* just after the MBR */
/* USB */
#ifdef CONFIG_CMD_USB
#define CONFIG_USB_DWC2_REG_ADDR SOCFPGA_USB1_ADDRESS
#endif
#define CONFIG_G_DNL_MANUFACTURER "Altera"
/* Extra Environment */
#define CONFIG_HOSTNAME socfpga_arria5
#define CONFIG_EXTRA_ENV_SETTINGS \
"verify=n\0" \
"loadaddr= " __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \

19
include/configs/socfpga_common.h
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@@ -3,8 +3,8 @@
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __CONFIG_SOCFPGA_CYCLONE5_COMMON_H__
#define __CONFIG_SOCFPGA_CYCLONE5_COMMON_H__
#ifndef __CONFIG_SOCFPGA_COMMON_H__
#define __CONFIG_SOCFPGA_COMMON_H__
/* Virtual target or real hardware */
@@ -69,6 +69,10 @@
#define CONFIG_CMDLINE_EDITING /* Command history etc */
#define CONFIG_SYS_HUSH_PARSER
#ifndef CONFIG_SYS_HOSTNAME
#define CONFIG_SYS_HOSTNAME CONFIG_SYS_BOARD
#endif
/*
* Cache
*/
@@ -229,13 +233,6 @@ unsigned int cm_get_qspi_controller_clk_hz(void);
#ifdef CONFIG_CMD_USB
#define CONFIG_USB_DWC2
#define CONFIG_USB_STORAGE
/*
* NOTE: User must define either of the following to select which
* of the two USB controllers available on SoCFPGA to use.
* The DWC2 driver doesn't support multiple USB controllers.
* #define CONFIG_USB_DWC2_REG_ADDR SOCFPGA_USB0_ADDRESS
* #define CONFIG_USB_DWC2_REG_ADDR SOCFPGA_USB1_ADDRESS
*/
#endif
/*
@@ -262,7 +259,7 @@ unsigned int cm_get_qspi_controller_clk_hz(void);
#define CONFIG_G_DNL_UMS_VENDOR_NUM CONFIG_G_DNL_VENDOR_NUM
#define CONFIG_G_DNL_UMS_PRODUCT_NUM CONFIG_G_DNL_PRODUCT_NUM
#ifndef CONFIG_G_DNL_MANUFACTURER
#define CONFIG_G_DNL_MANUFACTURER "Altera"
#define CONFIG_G_DNL_MANUFACTURER CONFIG_SYS_VENDOR
#endif
#endif
@@ -326,4 +323,4 @@ unsigned int cm_get_qspi_controller_clk_hz(void);
*/
#define CONFIG_SPL_STACK CONFIG_SYS_INIT_SP_ADDR
#endif /* __CONFIG_SOCFPGA_CYCLONE5_COMMON_H__ */
#endif /* __CONFIG_SOCFPGA_COMMON_H__ */

15
include/configs/socfpga_cyclone5_socdk.h
View File

@@ -47,30 +47,15 @@
/* Ethernet on SoC (EMAC) */
#if defined(CONFIG_CMD_NET)
/* PHY */
#define CONFIG_PHY_MICREL
#define CONFIG_PHY_MICREL_KSZ9021
#define CONFIG_KSZ9021_CLK_SKEW_ENV "micrel-ksz9021-clk-skew"
#define CONFIG_KSZ9021_CLK_SKEW_VAL 0xf0f0
#define CONFIG_KSZ9021_DATA_SKEW_ENV "micrel-ksz9021-data-skew"
#define CONFIG_KSZ9021_DATA_SKEW_VAL 0x0
#endif
#define CONFIG_ENV_IS_IN_MMC
#define CONFIG_SYS_MMC_ENV_DEV 0 /* device 0 */
#define CONFIG_ENV_OFFSET 512 /* just after the MBR */
/* USB */
#ifdef CONFIG_CMD_USB
#define CONFIG_USB_DWC2_REG_ADDR SOCFPGA_USB1_ADDRESS
#endif
#define CONFIG_G_DNL_MANUFACTURER "Altera"
/* Extra Environment */
#define CONFIG_HOSTNAME socfpga_cyclone5
#define CONFIG_EXTRA_ENV_SETTINGS \
"verify=n\0" \
"loadaddr= " __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \

15
include/configs/socfpga_de0_nano_soc.h
View File

@@ -37,36 +37,21 @@
#define CONFIG_BOOTDELAY 3
#define CONFIG_BOOTFILE "fitImage"
#define CONFIG_BOOTARGS "console=ttyS0," __stringify(CONFIG_BAUDRATE)
#ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET
#define CONFIG_BOOTCOMMAND "run ramboot"
#else
#define CONFIG_BOOTCOMMAND "run mmcload; run mmcboot"
#endif
#define CONFIG_LOADADDR 0x01000000
#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
/* Ethernet on SoC (EMAC) */
#if defined(CONFIG_CMD_NET)
/* PHY */
#define CONFIG_PHY_MICREL
#define CONFIG_PHY_MICREL_KSZ9031
#endif
#define CONFIG_ENV_IS_IN_MMC
#define CONFIG_SYS_MMC_ENV_DEV 0 /* device 0 */
#define CONFIG_ENV_OFFSET 512 /* just after the MBR */
/* USB */
#ifdef CONFIG_CMD_USB
#define CONFIG_USB_DWC2_REG_ADDR SOCFPGA_USB1_ADDRESS
#endif
#define CONFIG_G_DNL_MANUFACTURER "Terasic"
/* Extra Environment */
#define CONFIG_HOSTNAME socfpga_de0_nano_soc
#define CONFIG_EXTRA_ENV_SETTINGS \
"loadaddr= " __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
"ramboot=setenv bootargs " CONFIG_BOOTARGS ";" \

8
include/configs/socfpga_mcvevk.h
View File

@@ -48,15 +48,7 @@
#define CONFIG_SYS_MMC_ENV_DEV 0 /* device 0 */
#define CONFIG_ENV_OFFSET 512 /* just after the MBR */
/* USB */
#ifdef CONFIG_CMD_USB
#define CONFIG_USB_DWC2_REG_ADDR SOCFPGA_USB1_ADDRESS
#endif
#define CONFIG_G_DNL_MANUFACTURER "DENX"
/* Extra Environment */
#define CONFIG_HOSTNAME mcvevk
#define CONFIG_EXTRA_ENV_SETTINGS \
"consdev=ttyS0\0" \
"baudrate=115200\0" \

19
include/configs/socfpga_sockit.h
View File

@@ -37,40 +37,21 @@
#define CONFIG_BOOTDELAY 3
#define CONFIG_BOOTFILE "fitImage"
#define CONFIG_BOOTARGS "console=ttyS0," __stringify(CONFIG_BAUDRATE)
#ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET
#define CONFIG_BOOTCOMMAND "run ramboot"
#else
#define CONFIG_BOOTCOMMAND "run mmcload; run mmcboot"
#endif
#define CONFIG_LOADADDR 0x01000000
#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
/* Ethernet on SoC (EMAC) */
#if defined(CONFIG_CMD_NET)
/* PHY */
#define CONFIG_PHY_MICREL
#define CONFIG_PHY_MICREL_KSZ9021
#define CONFIG_KSZ9021_CLK_SKEW_ENV "micrel-ksz9021-clk-skew"
#define CONFIG_KSZ9021_CLK_SKEW_VAL 0xf0f0
#define CONFIG_KSZ9021_DATA_SKEW_ENV "micrel-ksz9021-data-skew"
#define CONFIG_KSZ9021_DATA_SKEW_VAL 0x0
#endif
#define CONFIG_ENV_IS_IN_MMC
#define CONFIG_SYS_MMC_ENV_DEV 0 /* device 0 */
#define CONFIG_ENV_OFFSET 512 /* just after the MBR */
/* USB */
#ifdef CONFIG_CMD_USB
#define CONFIG_USB_DWC2_REG_ADDR SOCFPGA_USB1_ADDRESS
#endif
#define CONFIG_G_DNL_MANUFACTURER "Terasic"
/* Extra Environment */
#define CONFIG_HOSTNAME socfpga_sockit
#define CONFIG_EXTRA_ENV_SETTINGS \
"verify=n\0" \
"loadaddr= " __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \

15
include/configs/socfpga_socrates.h
View File

@@ -43,30 +43,15 @@
/* Ethernet on SoC (EMAC) */
#if defined(CONFIG_CMD_NET)
/* PHY */
#define CONFIG_PHY_MICREL
#define CONFIG_PHY_MICREL_KSZ9021
#define CONFIG_KSZ9021_CLK_SKEW_ENV "micrel-ksz9021-clk-skew"
#define CONFIG_KSZ9021_CLK_SKEW_VAL 0xf0f0
#define CONFIG_KSZ9021_DATA_SKEW_ENV "micrel-ksz9021-data-skew"
#define CONFIG_KSZ9021_DATA_SKEW_VAL 0x0
#endif
#define CONFIG_ENV_IS_IN_MMC
#define CONFIG_SYS_MMC_ENV_DEV 0 /* device 0 */
#define CONFIG_ENV_OFFSET 512 /* just after the MBR */
/* USB */
#ifdef CONFIG_CMD_USB
#define CONFIG_USB_DWC2_REG_ADDR SOCFPGA_USB1_ADDRESS
#endif
#define CONFIG_G_DNL_MANUFACTURER "EBV"
/* Extra Environment */
#define CONFIG_HOSTNAME socfpga_socrates
#define CONFIG_EXTRA_ENV_SETTINGS \
"verify=n\0" \
"loadaddr= " __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \

3
include/configs/socfpga_sr1500.h
View File

@@ -53,9 +53,6 @@
#define CONFIG_PHY_MARVELL
#define PHY_ANEG_TIMEOUT 8000
/* Extra Environment */
#define CONFIG_HOSTNAME sr1500
#define CONFIG_EXTRA_ENV_SETTINGS \
"verify=n\0" \
"loadaddr= " __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \

1
include/fdtdec.h
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@@ -167,6 +167,7 @@ enum fdt_compat_id {
COMPAT_INTEL_IRQ_ROUTER, /* Intel Interrupt Router */
COMPAT_ALTERA_SOCFPGA_DWMAC, /* SoCFPGA Ethernet controller */
COMPAT_ALTERA_SOCFPGA_DWMMC, /* SoCFPGA DWMMC controller */
COMPAT_ALTERA_SOCFPGA_DWC2USB, /* SoCFPGA DWC2 USB controller */
COMPAT_INTEL_BAYTRAIL_FSP, /* Intel Bay Trail FSP */
COMPAT_INTEL_BAYTRAIL_FSP_MDP, /* Intel FSP memory-down params */