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Merge branch 'master' of git://git.denx.de/u-boot-mpc83xx

Browse Source 
* 'master' of git://git.denx.de/u-boot-mpc83xx:
  mpc8313erdb: fix mtdparts address
  powerpc/83xx/km: add support for 8321 based tuge1 board
  powerpc/83xx/km: merge tuxa and tuda1 boards to tuxx1
  powerpc/83xx/km: remove obsolete defines for tuda1
  powerpc/83xx/km: update SDRAM parameters for km8321 boards
  mpc8313erdb: Enable GPIO support on the MPC8313E RDB
  mpc83xx: Add a GPIO driver for the MPC83XX family
  gpio: Replace ARM gpio.h with the common API in include/asm-generic
  gpio: Modify common gpio.h to more closely match Linux
This commit is contained in:
Wolfgang Denk
2012-01-13 20:07:40 +01:00
parent 8eee2bd7f4 c947c12e78
commit 3dc5ea500f
20 changed files with 600 additions and 447 deletions
Download Patch File Download Diff File Expand all files Collapse all files

43
include/asm-generic/gpio.h
View File

@@ -1,5 +1,6 @@
/*
* Copyright (c) 2011 The Chromium OS Authors.
* Copyright (c) 2011, NVIDIA Corp. All rights reserved.
* See file CREDITS for list of people who contributed to this
* project.
*
@@ -19,6 +20,9 @@
* MA 02111-1307 USA
*/
#ifndef _ASM_GENERIC_GPIO_H_
#define _ASM_GENERIC_GPIO_H_
/*
* Generic GPIO API for U-Boot
*
@@ -38,37 +42,56 @@
*/
/**
* Make a GPIO an input.
* Request ownership of a GPIO.
*
* @param gp GPIO number
* @param gpio GPIO number
* @param label Name given to the GPIO
* @return 0 if ok, -1 on error
*/
int gpio_direction_input(int gp);
int gpio_request(unsigned gpio, const char *label);
/**
* Stop using the GPIO. This function should not alter pin configuration.
*
* @param gpio GPIO number
* @return 0 if ok, -1 on error
*/
int gpio_free(unsigned gpio);
/**
* Make a GPIO an input.
*
* @param gpio GPIO number
* @return 0 if ok, -1 on error
*/
int gpio_direction_input(unsigned gpio);
/**
* Make a GPIO an output, and set its value.
*
* @param gp GPIO number
* @param gpio GPIO number
* @param value GPIO value (0 for low or 1 for high)
* @return 0 if ok, -1 on error
*/
int gpio_direction_output(int gp, int value);
int gpio_direction_output(unsigned gpio, int value);
/**
* Get a GPIO's value. This will work whether the GPIO is an input
* or an output.
*
* @param gp GPIO number
* @param gpio GPIO number
* @return 0 if low, 1 if high, -1 on error
*/
int gpio_get_value(int gp);
int gpio_get_value(unsigned gpio);
/**
* Set an output GPIO's value. The GPIO must already be an output of
* Set an output GPIO's value. The GPIO must already be an output or
* this function may have no effect.
*
* @param gp GPIO number
* @param gpio GPIO number
* @param value GPIO value (0 for low or 1 for high)
* @return 0 if ok, -1 on error
*/
int gpio_set_value(int gp, int value);
int gpio_set_value(unsigned gpio, int value);
#endif /* _ASM_GENERIC_GPIO_H_ */

11
include/configs/MPC8313ERDB.h
View File

@@ -82,7 +82,8 @@
#define CONFIG_SYS_CLK_FREQ CONFIG_83XX_CLKIN
#define CONFIG_BOARD_EARLY_INIT_F /* call board_pre_init */
#define CONFIG_BOARD_EARLY_INIT_F /* call board_early_init_f */
#define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r */
#define CONFIG_SYS_IMMR 0xE0000000
@@ -266,7 +267,7 @@
#define CONFIG_CMD_MTDPARTS
#define MTDIDS_DEFAULT "nand0=e2800000.flash"
#define MTDPARTS_DEFAULT \
"mtdparts=e0600000.flash:512k(uboot),128k(env),3m@1m(kernel),-(fs)"
"mtdparts=e2800000.flash:512k(uboot),128k(env),3m@1m(kernel),-(fs)"
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_MTD_NAND_VERIFY_WRITE
@@ -363,6 +364,9 @@
#define CONFIG_OF_BOARD_SETUP 1
#define CONFIG_OF_STDOUT_VIA_ALIAS 1
#define CONFIG_MPC83XX_GPIO 1
#define CONFIG_CMD_GPIO 1
/*
* Serial Port
*/
@@ -581,7 +585,8 @@
/* System IO Config */
#define CONFIG_SYS_SICRH (SICRH_TSOBI1 | SICRH_TSOBI2) /* RGMII */
#define CONFIG_SYS_SICRL SICRL_USBDR_10 /* Enable Internal USB Phy */
/* Enable Internal USB Phy and GPIO on LCD Connector */
#define CONFIG_SYS_SICRL (SICRL_USBDR_10 | SICRL_LBC)
#define CONFIG_SYS_HID0_INIT 0x000000000
#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \

24
include/configs/km/km8321-common.h
View File

@@ -70,7 +70,8 @@
#define CONFIG_SYS_DDR_CS0_BNDS 0x0000007f
#define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SDRAM_TYPE_DDR2 | \
SDRAM_CFG_32_BE | \
SDRAM_CFG_SREN)
SDRAM_CFG_SREN | \
SDRAM_CFG_HSE)
#define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000
#define CONFIG_SYS_DDR_CLK_CNTL (DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
@@ -82,7 +83,7 @@
CSCONFIG_ROW_BIT_13 | \
CSCONFIG_COL_BIT_10)
#define CONFIG_SYS_DDR_MODE 0x47860252
#define CONFIG_SYS_DDR_MODE 0x47860242
#define CONFIG_SYS_DDR_MODE2 0x8080c000
#define CONFIG_SYS_DDR_TIMING_0 ((2 << TIMING_CFG0_MRS_CYC_SHIFT) | \
@@ -94,20 +95,20 @@
(0 << TIMING_CFG0_WRT_SHIFT) | \
(0 << TIMING_CFG0_RWT_SHIFT))
#define CONFIG_SYS_DDR_TIMING_1 ((TIMING_CFG1_CASLAT_50) | \
#define CONFIG_SYS_DDR_TIMING_1 ((TIMING_CFG1_CASLAT_40) | \
(2 << TIMING_CFG1_WRTORD_SHIFT) | \
(2 << TIMING_CFG1_ACTTOACT_SHIFT) | \
(2 << TIMING_CFG1_WRREC_SHIFT) | \
(6 << TIMING_CFG1_REFREC_SHIFT) | \
(2 << TIMING_CFG1_ACTTORW_SHIFT) | \
(6 << TIMING_CFG1_ACTTOPRE_SHIFT) | \
(2 << TIMING_CFG1_PRETOACT_SHIFT))
(3 << TIMING_CFG1_WRREC_SHIFT) | \
(7 << TIMING_CFG1_REFREC_SHIFT) | \
(3 << TIMING_CFG1_ACTTORW_SHIFT) | \
(7 << TIMING_CFG1_ACTTOPRE_SHIFT) | \
(3 << TIMING_CFG1_PRETOACT_SHIFT))
#define CONFIG_SYS_DDR_TIMING_2 ((8 << TIMING_CFG2_FOUR_ACT_SHIFT) | \
(3 << TIMING_CFG2_CKE_PLS_SHIFT) | \
(2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) | \
(2 << TIMING_CFG2_RD_TO_PRE_SHIFT) | \
(4 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) | \
(3 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) | \
(0 << TIMING_CFG2_ADD_LAT_SHIFT) | \
(5 << TIMING_CFG2_CPO_SHIFT))
@@ -122,7 +123,10 @@
/*
* Local Bus Configuration & Clock Setup
*/
#define CONFIG_SYS_LCRR (LCRR_DBYP | LCRR_EADC_1 | LCRR_CLKDIV_2)
#define CONFIG_SYS_LCRR_DBYP 0x80000000
#define CONFIG_SYS_LCRR_EADC 0x00010000
#define CONFIG_SYS_LCRR_CLKDIV 0x00000002
#define CONFIG_SYS_LBC_LBCR 0x00000000
/*

123
include/configs/tuxa1.h
View File

@@ -1,123 +0,0 @@
/*
* Copyright (C) 2006 Freescale Semiconductor, Inc.
* Dave Liu <daveliu@freescale.com>
*
* Copyright (C) 2007 Logic Product Development, Inc.
* Peter Barada <peterb@logicpd.com>
*
* Copyright (C) 2007 MontaVista Software, Inc.
* Anton Vorontsov <avorontsov@ru.mvista.com>
*
* (C) Copyright 2008
* Heiko Schocher, DENX Software Engineering, hs@denx.de.
*
* (C) Copyright 2010
* Yan Bin, Lukas Roggli, KEYMILE Ltd, lukas.roggli@keymile.com
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*/
#ifndef __CONFIG_H
#define __CONFIG_H
/*
* High Level Configuration Options
*/
#define CONFIG_TUXA1 /* TUXA1 board specific */
#define CONFIG_HOSTNAME tuxa1
#define CONFIG_KM_BOARD_NAME "tuxa1"
#define CONFIG_SYS_TEXT_BASE 0xF0000000
/* include common defines/options for all 8321 Keymile boards */
#include "km/km8321-common.h"
#define CONFIG_SYS_LPXF_BASE 0xA0000000 /* LPXF */
#define CONFIG_SYS_LPXF_SIZE 256 /* Megabytes */
#define CONFIG_SYS_PINC2_BASE 0xB0000000 /* PINC2 */
#define CONFIG_SYS_PINC2_SIZE 256 /* Megabytes */
/*
* Init Local Bus Memory Controller:
*
* Bank Bus Machine PortSz Size Device
* ---- --- ------- ------ ----- ------
* 2 Local GPCM 8 bit 256MB LPXF
* 3 Local GPCM 8 bit 256MB PINC2
*
*/
/*
* LPXF on the local bus CS2
* Window base at flash base
* Window size: 256 MB
*/
#define CONFIG_SYS_LBLAWBAR2_PRELIM CONFIG_SYS_LPXF_BASE
#define CONFIG_SYS_LBLAWAR2_PRELIM (LBLAWAR_EN | LBLAWAR_256MB)
#define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_LPXF_BASE | \
BR_PS_8 | \
BR_MS_GPCM | \
BR_V)
#define CONFIG_SYS_OR2_PRELIM (MEG_TO_AM(CONFIG_SYS_LPXF_SIZE) | \
OR_GPCM_CSNT | \
OR_GPCM_ACS_DIV4 | \
OR_GPCM_SCY_2 | \
OR_GPCM_TRLX_SET | \
OR_GPCM_EHTR_CLEAR | \
OR_GPCM_EAD)
/*
* PINC2 on the local bus CS3
* Access window base at PINC2 base
* Window size: 256 MB
*/
#define CONFIG_SYS_LBLAWBAR3_PRELIM CONFIG_SYS_PINC2_BASE
#define CONFIG_SYS_LBLAWAR3_PRELIM (LBLAWAR_EN | LBLAWAR_256MB)
#define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_PINC2_BASE | \
BR_PS_8 | \
BR_MS_GPCM | \
BR_V)
#define CONFIG_SYS_OR3_PRELIM (MEG_TO_AM(CONFIG_SYS_PINC2_SIZE) | \
OR_GPCM_CSNT | \
OR_GPCM_ACS_DIV2 | \
OR_GPCM_SCY_2 | \
OR_GPCM_TRLX_SET | \
OR_GPCM_EHTR_CLEAR)
#define CONFIG_SYS_MAMR (MxMR_GPL_x4DIS | \
0x0000c000 | \
MxMR_WLFx_2X)
/*
* MMU Setup
*/
/* LPXF: icache cacheable, but dcache-inhibit and guarded */
#define CONFIG_SYS_IBAT5L (CONFIG_SYS_LPXF_BASE | BATL_PP_RW | \
BATL_MEMCOHERENCE)
#define CONFIG_SYS_IBAT5U (CONFIG_SYS_LPXF_BASE | BATU_BL_256M | \
BATU_VS | BATU_VP)
#define CONFIG_SYS_DBAT5L (CONFIG_SYS_LPXF_BASE | BATL_PP_RW | \
BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
/* PINC2: icache cacheable, but dcache-inhibit and guarded */
#define CONFIG_SYS_IBAT6L (CONFIG_SYS_PINC2_BASE | BATL_PP_RW | \
BATL_MEMCOHERENCE)
#define CONFIG_SYS_IBAT6U (CONFIG_SYS_PINC2_BASE | BATU_BL_256M | \
BATU_VS | BATU_VP)
#define CONFIG_SYS_DBAT6L (CONFIG_SYS_PINC2_BASE | BATL_PP_RW | \
BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
#define CONFIG_SYS_IBAT7L (0)
#define CONFIG_SYS_IBAT7U (0)
#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
#endif /* __CONFIG_H */

43
include/configs/tuda1.h → include/configs/tuxx1.h
View File

@@ -13,6 +13,7 @@
*
* (C) Copyright 2010-2011
* Lukas Roggli, KEYMILE Ltd, lukas.roggli@keymile.com
* Holger Brunck, Keymile GmbH, holger.bruncl@keymile.com
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
@@ -26,9 +27,13 @@
/*
* High Level Configuration Options
*/
#define CONFIG_TUDA1 /* TUDA1 board specific */
#define CONFIG_HOSTNAME tuda1
#define CONFIG_KM_BOARD_NAME "tuda1"
#define CONFIG_TUXXX /* TUXX1 board (tuxa1/tuda1) specific */
#define CONFIG_HOSTNAME tuxx1
#ifdef CONFIG_KM_DISABLE_APP2
#define CONFIG_KM_BOARD_NAME "tuge1"
#else
#define CONFIG_KM_BOARD_NAME "tuxx1"
#endif
#define CONFIG_SYS_TEXT_BASE 0xF0000000
@@ -37,27 +42,23 @@
#define CONFIG_SYS_APP1_BASE 0xA0000000 /* PAXG */
#define CONFIG_SYS_APP1_SIZE 256 /* Megabytes */
#ifndef CONFIG_KM_DISABLE_APP2
#define CONFIG_SYS_APP2_BASE 0xB0000000 /* PINC3 */
#define CONFIG_SYS_APP2_SIZE 256 /* Megabytes */
/*
* Local Bus Configuration & Clock Setup
*/
#define CONFIG_SYS_LCRR (LCRR_DBYP | LCRR_EADC_1 | LCRR_CLKDIV_2)
#define CONFIG_SYS_LBC_LBCR 0x00000000
#endif
/*
* Init Local Bus Memory Controller:
*
* Bank Bus Machine PortSz Size Device
* ---- --- ------- ------ ----- ------
* 2 Local GPCM 8 bit 256MB PAXG
* 3 Local GPCM 8 bit 256MB PINC3
* Bank Bus Machine PortSz Size Device on TUDA1 TUXA1 TUGE1
* ---- --- ------- ------ ----- ----------------------------
* 2 Local GPCM 8 bit 256MB PAXG LPXF PAXI
* 3 Local GPCM 8 bit 256MB PINC3 PINC2 unused
*
*/
/*
* PAXG on the local bus CS2
* Configuration for C2 on the local bus
*/
/* Window base at flash base */
#define CONFIG_SYS_LBLAWBAR2_PRELIM CONFIG_SYS_APP1_BASE
@@ -76,8 +77,9 @@
OR_GPCM_TRLX_SET | \
OR_GPCM_EHTR_CLEAR | \
OR_GPCM_EAD)
#ifndef CONFIG_KM_DISABLE_APP2
/*
* PINC3 on the local bus CS3
* Configuration for C3 on the local bus
*/
/* Access window base at PINC3 base */
#define CONFIG_SYS_LBLAWBAR3_PRELIM CONFIG_SYS_APP2_BASE
@@ -99,11 +101,12 @@
#define CONFIG_SYS_MAMR (MxMR_GPL_x4DIS | \
0x0000c000 | \
MxMR_WLFx_2X)
#endif
/*
* MMU Setup
*/
/* PAXG: icache cacheable, but dcache-inhibit and guarded */
/* APP1: icache cacheable, but dcache-inhibit and guarded */
#define CONFIG_SYS_IBAT5L (CONFIG_SYS_APP1_BASE | \
BATL_PP_RW | \
BATL_MEMCOHERENCE)
@@ -118,7 +121,12 @@
BATL_GUARDEDSTORAGE)
#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
/* PINC3: icache cacheable, but dcache-inhibit and guarded */
#ifdef CONFIG_KM_DISABLE_APP2
#define CONFIG_SYS_IBAT6L (0)
#define CONFIG_SYS_IBAT6U (0)
#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
#else
/* APP2: icache cacheable, but dcache-inhibit and guarded */
#define CONFIG_SYS_IBAT6L (CONFIG_SYS_APP2_BASE | \
BATL_PP_RW | \
BATL_MEMCOHERENCE)
@@ -130,6 +138,7 @@
BATL_PP_RW | \
BATL_CACHEINHIBIT | \
BATL_GUARDEDSTORAGE)
#endif
#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
#define CONFIG_SYS_IBAT7L (0)