Merge branch 'master' of git://git.denx.de/u-boot-video
This commit is contained in:
Tom Rini
@@ -36,6 +36,9 @@ int display_read_timing(struct udevice *dev, struct display_timing *timing)
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u8 buf[EDID_EXT_SIZE];
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int ret;
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if (ops && ops->read_timing)
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return ops->read_timing(dev, timing);
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if (!ops || !ops->read_edid)
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return -ENOSYS;
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ret = ops->read_edid(dev, buf, sizeof(buf));
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@@ -19,6 +19,7 @@
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#include <asm/errno.h>
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#include <asm/arch/imx-regs.h>
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#include <asm/arch/crm_regs.h>
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#include <div64.h>
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#include "ipu.h"
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#include "ipu_regs.h"
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@@ -275,50 +276,84 @@ static inline void ipu_ch_param_set_buffer(uint32_t ch, int bufNum,
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static void ipu_pixel_clk_recalc(struct clk *clk)
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{
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u32 div = __raw_readl(DI_BS_CLKGEN0(clk->id));
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if (div == 0)
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clk->rate = 0;
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else
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clk->rate = (clk->parent->rate * 16) / div;
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u32 div;
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u64 final_rate = (unsigned long long)clk->parent->rate * 16;
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div = __raw_readl(DI_BS_CLKGEN0(clk->id));
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debug("read BS_CLKGEN0 div:%d, final_rate:%lld, prate:%ld\n",
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div, final_rate, clk->parent->rate);
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clk->rate = 0;
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if (div != 0) {
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do_div(final_rate, div);
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clk->rate = final_rate;
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}
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}
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static unsigned long ipu_pixel_clk_round_rate(struct clk *clk,
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unsigned long rate)
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{
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u32 div, div1;
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u32 tmp;
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u64 div, final_rate;
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u32 remainder;
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u64 parent_rate = (unsigned long long)clk->parent->rate * 16;
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/*
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* Calculate divider
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* Fractional part is 4 bits,
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* so simply multiply by 2^4 to get fractional part.
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*/
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tmp = (clk->parent->rate * 16);
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div = tmp / rate;
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div = parent_rate;
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remainder = do_div(div, rate);
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/* Round the divider value */
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if (remainder > (rate / 2))
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div++;
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if (div < 0x10) /* Min DI disp clock divider is 1 */
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div = 0x10;
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if (div & ~0xFEF)
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div &= 0xFF8;
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else {
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div1 = div & 0xFE0;
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if ((tmp/div1 - tmp/div) < rate / 4)
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div = div1;
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else
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div &= 0xFF8;
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/* Round up divider if it gets us closer to desired pix clk */
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if ((div & 0xC) == 0xC) {
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div += 0x10;
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div &= ~0xF;
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}
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}
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return (clk->parent->rate * 16) / div;
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final_rate = parent_rate;
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do_div(final_rate, div);
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return final_rate;
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}
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static int ipu_pixel_clk_set_rate(struct clk *clk, unsigned long rate)
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{
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u32 div = (clk->parent->rate * 16) / rate;
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u64 div, parent_rate;
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u32 remainder;
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parent_rate = (unsigned long long)clk->parent->rate * 16;
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div = parent_rate;
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remainder = do_div(div, rate);
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/* Round the divider value */
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if (remainder > (rate / 2))
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div++;
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/* Round up divider if it gets us closer to desired pix clk */
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if ((div & 0xC) == 0xC) {
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div += 0x10;
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div &= ~0xF;
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}
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if (div > 0x1000)
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debug("Overflow, DI_BS_CLKGEN0 div:0x%x\n", (u32)div);
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__raw_writel(div, DI_BS_CLKGEN0(clk->id));
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/* Setup pixel clock timing */
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/*
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* Setup pixel clock timing
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* Down time is half of period
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*/
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__raw_writel((div / 16) << 16, DI_BS_CLKGEN1(clk->id));
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clk->rate = (clk->parent->rate * 16) / div;
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clk->rate = (u64)(clk->parent->rate * 16) / div;
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return 0;
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}
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@@ -5,4 +5,4 @@
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# SPDX-License-Identifier: GPL-2.0+
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#
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obj-y += rk_edp.o rk_hdmi.o rk_vop.o
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obj-y += rk_edp.o rk_hdmi.o rk_vop.o rk_lvds.o
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254
drivers/video/rockchip/rk_lvds.c
Normal file
254
drivers/video/rockchip/rk_lvds.c
Normal file
@@ -0,0 +1,254 @@
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/*
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* Copyright 2016 Rockchip Inc.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <clk.h>
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#include <display.h>
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#include <dm.h>
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#include <edid.h>
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#include <panel.h>
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#include <regmap.h>
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#include <syscon.h>
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#include <asm/gpio.h>
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#include <asm/io.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/lvds_rk3288.h>
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#include <asm/arch/grf_rk3288.h>
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#include <dt-bindings/clock/rk3288-cru.h>
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#include <dt-bindings/video/rk3288.h>
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DECLARE_GLOBAL_DATA_PTR;
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/**
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* struct rk_lvds_priv - private rockchip lvds display driver info
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*
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* @reg: LVDS register address
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* @grf: GRF register
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* @panel: Panel device that is used in driver
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*
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* @output: Output mode, decided single or double channel,
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* LVDS or LVTLL
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* @format: Data format that RGB data will packing as
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*/
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struct rk_lvds_priv {
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void __iomem *regs;
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struct rk3288_grf *grf;
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struct udevice *panel;
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int output;
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int format;
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};
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static inline void lvds_writel(struct rk_lvds_priv *lvds, u32 offset, u32 val)
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{
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writel(val, lvds->regs + offset);
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writel(val, lvds->regs + offset + 0x100);
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}
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int rk_lvds_enable(struct udevice *dev, int panel_bpp,
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const struct display_timing *edid)
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{
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struct rk_lvds_priv *priv = dev_get_priv(dev);
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struct display_plat *uc_plat = dev_get_uclass_platdata(dev);
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int ret = 0;
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unsigned int val = 0;
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ret = panel_enable_backlight(priv->panel);
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if (ret) {
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debug("%s: backlight error: %d\n", __func__, ret);
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return ret;
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}
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/* Select the video source */
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if (uc_plat->source_id)
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val = RK3288_LVDS_SOC_CON6_SEL_VOP_LIT |
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(RK3288_LVDS_SOC_CON6_SEL_VOP_LIT << 16);
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else
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val = RK3288_LVDS_SOC_CON6_SEL_VOP_LIT << 16;
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rk_setreg(&priv->grf->soc_con6, val);
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/* Select data transfer format */
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val = priv->format;
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if (priv->output == LVDS_OUTPUT_DUAL)
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val |= LVDS_DUAL | LVDS_CH0_EN | LVDS_CH1_EN;
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else if (priv->output == LVDS_OUTPUT_SINGLE)
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val |= LVDS_CH0_EN;
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else if (priv->output == LVDS_OUTPUT_RGB)
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val |= LVDS_TTL_EN | LVDS_CH0_EN | LVDS_CH1_EN;
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val |= (0xffff << 16);
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rk_setreg(&priv->grf->soc_con7, val);
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/* Enable LVDS PHY */
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if (priv->output == LVDS_OUTPUT_RGB) {
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lvds_writel(priv, RK3288_LVDS_CH0_REG0,
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RK3288_LVDS_CH0_REG0_TTL_EN |
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RK3288_LVDS_CH0_REG0_LANECK_EN |
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RK3288_LVDS_CH0_REG0_LANE4_EN |
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RK3288_LVDS_CH0_REG0_LANE3_EN |
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RK3288_LVDS_CH0_REG0_LANE2_EN |
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RK3288_LVDS_CH0_REG0_LANE1_EN |
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RK3288_LVDS_CH0_REG0_LANE0_EN);
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lvds_writel(priv, RK3288_LVDS_CH0_REG2,
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RK3288_LVDS_PLL_FBDIV_REG2(0x46));
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lvds_writel(priv, RK3288_LVDS_CH0_REG3,
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RK3288_LVDS_PLL_FBDIV_REG3(0x46));
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lvds_writel(priv, RK3288_LVDS_CH0_REG4,
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RK3288_LVDS_CH0_REG4_LANECK_TTL_MODE |
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RK3288_LVDS_CH0_REG4_LANE4_TTL_MODE |
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RK3288_LVDS_CH0_REG4_LANE3_TTL_MODE |
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RK3288_LVDS_CH0_REG4_LANE2_TTL_MODE |
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RK3288_LVDS_CH0_REG4_LANE1_TTL_MODE |
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RK3288_LVDS_CH0_REG4_LANE0_TTL_MODE);
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lvds_writel(priv, RK3288_LVDS_CH0_REG5,
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RK3288_LVDS_CH0_REG5_LANECK_TTL_DATA |
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RK3288_LVDS_CH0_REG5_LANE4_TTL_DATA |
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RK3288_LVDS_CH0_REG5_LANE3_TTL_DATA |
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RK3288_LVDS_CH0_REG5_LANE2_TTL_DATA |
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RK3288_LVDS_CH0_REG5_LANE1_TTL_DATA |
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RK3288_LVDS_CH0_REG5_LANE0_TTL_DATA);
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lvds_writel(priv, RK3288_LVDS_CH0_REGD,
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RK3288_LVDS_PLL_PREDIV_REGD(0x0a));
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lvds_writel(priv, RK3288_LVDS_CH0_REG20,
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RK3288_LVDS_CH0_REG20_LSB);
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} else {
|
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lvds_writel(priv, RK3288_LVDS_CH0_REG0,
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RK3288_LVDS_CH0_REG0_LVDS_EN |
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RK3288_LVDS_CH0_REG0_LANECK_EN |
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||||
RK3288_LVDS_CH0_REG0_LANE4_EN |
|
||||
RK3288_LVDS_CH0_REG0_LANE3_EN |
|
||||
RK3288_LVDS_CH0_REG0_LANE2_EN |
|
||||
RK3288_LVDS_CH0_REG0_LANE1_EN |
|
||||
RK3288_LVDS_CH0_REG0_LANE0_EN);
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lvds_writel(priv, RK3288_LVDS_CH0_REG1,
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RK3288_LVDS_CH0_REG1_LANECK_BIAS |
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||||
RK3288_LVDS_CH0_REG1_LANE4_BIAS |
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||||
RK3288_LVDS_CH0_REG1_LANE3_BIAS |
|
||||
RK3288_LVDS_CH0_REG1_LANE2_BIAS |
|
||||
RK3288_LVDS_CH0_REG1_LANE1_BIAS |
|
||||
RK3288_LVDS_CH0_REG1_LANE0_BIAS);
|
||||
lvds_writel(priv, RK3288_LVDS_CH0_REG2,
|
||||
RK3288_LVDS_CH0_REG2_RESERVE_ON |
|
||||
RK3288_LVDS_CH0_REG2_LANECK_LVDS_MODE |
|
||||
RK3288_LVDS_CH0_REG2_LANE4_LVDS_MODE |
|
||||
RK3288_LVDS_CH0_REG2_LANE3_LVDS_MODE |
|
||||
RK3288_LVDS_CH0_REG2_LANE2_LVDS_MODE |
|
||||
RK3288_LVDS_CH0_REG2_LANE1_LVDS_MODE |
|
||||
RK3288_LVDS_CH0_REG2_LANE0_LVDS_MODE |
|
||||
RK3288_LVDS_PLL_FBDIV_REG2(0x46));
|
||||
lvds_writel(priv, RK3288_LVDS_CH0_REG3,
|
||||
RK3288_LVDS_PLL_FBDIV_REG3(0x46));
|
||||
lvds_writel(priv, RK3288_LVDS_CH0_REG4, 0x00);
|
||||
lvds_writel(priv, RK3288_LVDS_CH0_REG5, 0x00);
|
||||
lvds_writel(priv, RK3288_LVDS_CH0_REGD,
|
||||
RK3288_LVDS_PLL_PREDIV_REGD(0x0a));
|
||||
lvds_writel(priv, RK3288_LVDS_CH0_REG20,
|
||||
RK3288_LVDS_CH0_REG20_LSB);
|
||||
}
|
||||
|
||||
/* Power on */
|
||||
writel(RK3288_LVDS_CFG_REGC_PLL_ENABLE,
|
||||
priv->regs + RK3288_LVDS_CFG_REGC);
|
||||
|
||||
writel(RK3288_LVDS_CFG_REG21_TX_ENABLE,
|
||||
priv->regs + RK3288_LVDS_CFG_REG21);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int rk_lvds_read_timing(struct udevice *dev, struct display_timing *timing)
|
||||
{
|
||||
if (fdtdec_decode_display_timing
|
||||
(gd->fdt_blob, dev->of_offset, 0, timing)) {
|
||||
debug("%s: Failed to decode display timing\n", __func__);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int rk_lvds_ofdata_to_platdata(struct udevice *dev)
|
||||
{
|
||||
struct rk_lvds_priv *priv = dev_get_priv(dev);
|
||||
const void *blob = gd->fdt_blob;
|
||||
int node = dev->of_offset;
|
||||
int ret;
|
||||
priv->regs = (void *)dev_get_addr(dev);
|
||||
priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
|
||||
|
||||
ret = fdtdec_get_int(blob, node, "rockchip,output", -1);
|
||||
if (ret != -1) {
|
||||
priv->output = ret;
|
||||
debug("LVDS output : %d\n", ret);
|
||||
} else {
|
||||
/* default set it as output rgb */
|
||||
priv->output = LVDS_OUTPUT_RGB;
|
||||
}
|
||||
|
||||
ret = fdtdec_get_int(blob, node, "rockchip,data-mapping", -1);
|
||||
if (ret != -1) {
|
||||
priv->format = ret;
|
||||
debug("LVDS data-mapping : %d\n", ret);
|
||||
} else {
|
||||
/* default set it as format jeida */
|
||||
priv->format = LVDS_FORMAT_JEIDA;
|
||||
}
|
||||
|
||||
ret = fdtdec_get_int(blob, node, "rockchip,data-width", -1);
|
||||
if (ret != -1) {
|
||||
debug("LVDS data-width : %d\n", ret);
|
||||
if (ret == 24) {
|
||||
priv->format |= LVDS_24BIT;
|
||||
} else if (ret == 18) {
|
||||
priv->format |= LVDS_18BIT;
|
||||
} else {
|
||||
debug("rockchip-lvds unsupport data-width[%d]\n", ret);
|
||||
ret = -EINVAL;
|
||||
return ret;
|
||||
}
|
||||
} else {
|
||||
priv->format |= LVDS_24BIT;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int rk_lvds_probe(struct udevice *dev)
|
||||
{
|
||||
struct rk_lvds_priv *priv = dev_get_priv(dev);
|
||||
int ret;
|
||||
|
||||
ret = uclass_get_device_by_phandle(UCLASS_PANEL, dev, "rockchip,panel",
|
||||
&priv->panel);
|
||||
if (ret) {
|
||||
debug("%s: Cannot find panel for '%s' (ret=%d)\n", __func__,
|
||||
dev->name, ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct dm_display_ops lvds_rockchip_ops = {
|
||||
.read_timing = rk_lvds_read_timing,
|
||||
.enable = rk_lvds_enable,
|
||||
};
|
||||
|
||||
static const struct udevice_id rockchip_lvds_ids[] = {
|
||||
{.compatible = "rockchip,rk3288-lvds"},
|
||||
{}
|
||||
};
|
||||
|
||||
U_BOOT_DRIVER(lvds_rockchip) = {
|
||||
.name = "lvds_rockchip",
|
||||
.id = UCLASS_DISPLAY,
|
||||
.of_match = rockchip_lvds_ids,
|
||||
.ops = &lvds_rockchip_ops,
|
||||
.ofdata_to_platdata = rk_lvds_ofdata_to_platdata,
|
||||
.probe = rk_lvds_probe,
|
||||
.priv_auto_alloc_size = sizeof(struct rk_lvds_priv),
|
||||
};
|
||||
@@ -102,6 +102,7 @@ void rkvop_mode_set(struct rk3288_vop *regs,
|
||||
u32 hfront_porch = edid->hfront_porch.typ;
|
||||
u32 vfront_porch = edid->vfront_porch.typ;
|
||||
uint flags;
|
||||
int mode_flags;
|
||||
|
||||
switch (mode) {
|
||||
case VOP_MODE_HDMI:
|
||||
@@ -113,9 +114,20 @@ void rkvop_mode_set(struct rk3288_vop *regs,
|
||||
clrsetbits_le32(®s->sys_ctrl, M_ALL_OUT_EN,
|
||||
V_EDP_OUT_EN(1));
|
||||
break;
|
||||
case VOP_MODE_LVDS:
|
||||
clrsetbits_le32(®s->sys_ctrl, M_ALL_OUT_EN,
|
||||
V_RGB_OUT_EN(1));
|
||||
break;
|
||||
}
|
||||
|
||||
flags = V_DSP_OUT_MODE(15) |
|
||||
if (mode == VOP_MODE_HDMI || mode == VOP_MODE_EDP)
|
||||
/* RGBaaa */
|
||||
mode_flags = 15;
|
||||
else
|
||||
/* RGB888 */
|
||||
mode_flags = 0;
|
||||
|
||||
flags = V_DSP_OUT_MODE(mode_flags) |
|
||||
V_DSP_HSYNC_POL(!!(edid->flags & DISPLAY_FLAGS_HSYNC_HIGH)) |
|
||||
V_DSP_VSYNC_POL(!!(edid->flags & DISPLAY_FLAGS_VSYNC_HIGH));
|
||||
|
||||
@@ -227,7 +239,7 @@ int rk_display_init(struct udevice *dev, ulong fbbase,
|
||||
|
||||
ret = rkclk_get_clk(CLK_NEW, &clk);
|
||||
if (!ret) {
|
||||
ret = clk_set_periph_rate(clk, DCLK_VOP0 + vop_id,
|
||||
ret = clk_set_periph_rate(clk, DCLK_VOP0 + remote_vop_id,
|
||||
timing.pixelclock.typ);
|
||||
}
|
||||
if (ret) {
|
||||
|
||||
Reference in New Issue
Block a user