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Big white-space cleanup.

Browse Source 
This commit gets rid of a huge amount of silly white-space issues.
Especially, all sequences of SPACEs followed by TAB characters get
removed (unless they appear in print statements).

Also remove all embedded "vim:" and "vi:" statements which hide
indentation problems.

Signed-off-by: Wolfgang Denk <wd@denx.de>
This commit is contained in:
Wolfgang Denk
2008-05-20 16:00:29 +02:00
parent 727f633346
commit 53677ef18e
1010 changed files with 13324 additions and 13313 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
post/drivers/memory.c
View File

@@ -282,7 +282,7 @@ static int memory_post_addrline(ulong *testaddr, ulong *base, ulong size)
#endif
if(readback == *testaddr) {
post_log ("Memory (address line) error at %08x<->%08x, "
"XOR value %08x !\n",
"XOR value %08x !\n",
testaddr, target, xor);
ret = -1;
}

8
post/lib_ppc/andi.c
View File

@@ -49,13 +49,13 @@ static struct cpu_post_andi_s
} cpu_post_andi_table[] =
{
{
OP_ANDI_,
OP_ANDI_,
0x80008000,
0xffff,
0x00008000
},
{
OP_ANDIS_,
OP_ANDIS_,
0x80008000,
0xffff,
0x80000000
@@ -79,7 +79,7 @@ int cpu_post_test_andi (void)
unsigned int reg0 = (reg + 0) % 32;
unsigned int reg1 = (reg + 1) % 32;
unsigned int stk = reg < 16 ? 31 : 15;
unsigned long codecr[] =
unsigned long codecr[] =
{
ASM_STW(stk, 1, -4),
ASM_ADDI(stk, 1, -16),
@@ -112,7 +112,7 @@ int cpu_post_test_andi (void)
}
if (flag)
enable_interrupts();
enable_interrupts();
return ret;
}

2
post/lib_ppc/cmp.c
View File

@@ -106,7 +106,7 @@ int cpu_post_test_cmp (void)
for (i = 0; i < cpu_post_cmp_size && ret == 0; i++)
{
struct cpu_post_cmp_s *test = cpu_post_cmp_table + i;
unsigned long code[] =
unsigned long code[] =
{
ASM_2C(test->cmd, test->cr, 3, 4),
ASM_MFCR(3),

2
post/lib_ppc/cmpi.c
View File

@@ -106,7 +106,7 @@ int cpu_post_test_cmpi (void)
for (i = 0; i < cpu_post_cmpi_size && ret == 0; i++)
{
struct cpu_post_cmpi_s *test = cpu_post_cmpi_table + i;
unsigned long code[] =
unsigned long code[] =
{
ASM_1IC(test->cmd, test->cr, 3, test->op2),
ASM_MFCR(3),

2
post/lib_ppc/cpu_asm.h
View File

@@ -191,7 +191,7 @@
((imm2) << 6) + \
((imm3) << 1))
#define ASM_1O(opcode, off) ((opcode) + (off))
#define ASM_3O(opcode, bo, bi, off) ((opcode) + \
#define ASM_3O(opcode, bo, bi, off) ((opcode) + \
((bo) << 21) + \
((bi) << 16) + \
(off))

28
post/lib_ppc/rlwimi.c
View File

@@ -53,7 +53,7 @@ static struct cpu_post_rlwimi_s
} cpu_post_rlwimi_table[] =
{
{
OP_RLWIMI,
OP_RLWIMI,
0xff00ffff,
0x0000aa00,
8,
@@ -80,7 +80,7 @@ int cpu_post_test_rlwimi (void)
unsigned int reg0 = (reg + 0) % 32;
unsigned int reg1 = (reg + 1) % 32;
unsigned int stk = reg < 16 ? 31 : 15;
unsigned long code[] =
unsigned long code[] =
{
ASM_STW(stk, 1, -4),
ASM_ADDI(stk, 1, -20),
@@ -99,7 +99,7 @@ int cpu_post_test_rlwimi (void)
ASM_LWZ(stk, 1, -4),
ASM_BLR,
};
unsigned long codecr[] =
unsigned long codecr[] =
{
ASM_STW(stk, 1, -4),
ASM_ADDI(stk, 1, -20),
@@ -124,26 +124,26 @@ int cpu_post_test_rlwimi (void)
if (ret == 0)
{
cr = 0;
cpu_post_exec_22 (code, & cr, & res, test->op0, test->op1);
cr = 0;
cpu_post_exec_22 (code, & cr, & res, test->op0, test->op1);
ret = res == test->res && cr == 0 ? 0 : -1;
ret = res == test->res && cr == 0 ? 0 : -1;
if (ret != 0)
{
if (ret != 0)
{
post_log ("Error at rlwimi test %d !\n", i);
}
}
}
if (ret == 0)
{
cpu_post_exec_22 (codecr, & cr, & res, test->op0, test->op1);
cpu_post_exec_22 (codecr, & cr, & res, test->op0, test->op1);
ret = res == test->res &&
ret = res == test->res &&
(cr & 0xe0000000) == cpu_post_makecr (res) ? 0 : -1;
if (ret != 0)
{
if (ret != 0)
{
post_log ("Error at rlwimi test %d !\n", i);
}
}
@@ -151,7 +151,7 @@ int cpu_post_test_rlwimi (void)
}
if (flag)
enable_interrupts();
enable_interrupts();
return ret;
}

28
post/lib_ppc/rlwinm.c
View File

@@ -51,7 +51,7 @@ static struct cpu_post_rlwinm_s
} cpu_post_rlwinm_table[] =
{
{
OP_RLWINM,
OP_RLWINM,
0xffff0000,
24,
16,
@@ -77,7 +77,7 @@ int cpu_post_test_rlwinm (void)
unsigned int reg0 = (reg + 0) % 32;
unsigned int reg1 = (reg + 1) % 32;
unsigned int stk = reg < 16 ? 31 : 15;
unsigned long code[] =
unsigned long code[] =
{
ASM_STW(stk, 1, -4),
ASM_ADDI(stk, 1, -16),
@@ -94,7 +94,7 @@ int cpu_post_test_rlwinm (void)
ASM_LWZ(stk, 1, -4),
ASM_BLR,
};
unsigned long codecr[] =
unsigned long codecr[] =
{
ASM_STW(stk, 1, -4),
ASM_ADDI(stk, 1, -16),
@@ -117,26 +117,26 @@ int cpu_post_test_rlwinm (void)
if (ret == 0)
{
cr = 0;
cpu_post_exec_21 (code, & cr, & res, test->op1);
cr = 0;
cpu_post_exec_21 (code, & cr, & res, test->op1);
ret = res == test->res && cr == 0 ? 0 : -1;
ret = res == test->res && cr == 0 ? 0 : -1;
if (ret != 0)
{
if (ret != 0)
{
post_log ("Error at rlwinm test %d !\n", i);
}
}
}
if (ret == 0)
{
cpu_post_exec_21 (codecr, & cr, & res, test->op1);
cpu_post_exec_21 (codecr, & cr, & res, test->op1);
ret = res == test->res &&
ret = res == test->res &&
(cr & 0xe0000000) == cpu_post_makecr (res) ? 0 : -1;
if (ret != 0)
{
if (ret != 0)
{
post_log ("Error at rlwinm test %d !\n", i);
}
}
@@ -144,7 +144,7 @@ int cpu_post_test_rlwinm (void)
}
if (flag)
enable_interrupts();
enable_interrupts();
return ret;
}

28
post/lib_ppc/rlwnm.c
View File

@@ -52,7 +52,7 @@ static struct cpu_post_rlwnm_s
} cpu_post_rlwnm_table[] =
{
{
OP_RLWNM,
OP_RLWNM,
0xffff0000,
24,
16,
@@ -79,7 +79,7 @@ int cpu_post_test_rlwnm (void)
unsigned int reg1 = (reg + 1) % 32;
unsigned int reg2 = (reg + 2) % 32;
unsigned int stk = reg < 16 ? 31 : 15;
unsigned long code[] =
unsigned long code[] =
{
ASM_STW(stk, 1, -4),
ASM_ADDI(stk, 1, -24),
@@ -100,7 +100,7 @@ int cpu_post_test_rlwnm (void)
ASM_LWZ(stk, 1, -4),
ASM_BLR,
};
unsigned long codecr[] =
unsigned long codecr[] =
{
ASM_STW(stk, 1, -4),
ASM_ADDI(stk, 1, -24),
@@ -127,26 +127,26 @@ int cpu_post_test_rlwnm (void)
if (ret == 0)
{
cr = 0;
cpu_post_exec_22 (code, & cr, & res, test->op1, test->op2);
cr = 0;
cpu_post_exec_22 (code, & cr, & res, test->op1, test->op2);
ret = res == test->res && cr == 0 ? 0 : -1;
ret = res == test->res && cr == 0 ? 0 : -1;
if (ret != 0)
{
if (ret != 0)
{
post_log ("Error at rlwnm test %d !\n", i);
}
}
}
if (ret == 0)
{
cpu_post_exec_22 (codecr, & cr, & res, test->op1, test->op2);
cpu_post_exec_22 (codecr, & cr, & res, test->op1, test->op2);
ret = res == test->res &&
ret = res == test->res &&
(cr & 0xe0000000) == cpu_post_makecr (res) ? 0 : -1;
if (ret != 0)
{
if (ret != 0)
{
post_log ("Error at rlwnm test %d !\n", i);
}
}
@@ -154,7 +154,7 @@ int cpu_post_test_rlwnm (void)
}
if (flag)
enable_interrupts();
enable_interrupts();
return ret;
}

30
post/lib_ppc/srawi.c
View File

@@ -49,13 +49,13 @@ static struct cpu_post_srawi_s
} cpu_post_srawi_table[] =
{
{
OP_SRAWI,
OP_SRAWI,
0x8000,
3,
0x1000
},
{
OP_SRAWI,
OP_SRAWI,
0x80000000,
3,
0xf0000000
@@ -79,7 +79,7 @@ int cpu_post_test_srawi (void)
unsigned int reg0 = (reg + 0) % 32;
unsigned int reg1 = (reg + 1) % 32;
unsigned int stk = reg < 16 ? 31 : 15;
unsigned long code[] =
unsigned long code[] =
{
ASM_STW(stk, 1, -4),
ASM_ADDI(stk, 1, -16),
@@ -96,7 +96,7 @@ int cpu_post_test_srawi (void)
ASM_LWZ(stk, 1, -4),
ASM_BLR,
};
unsigned long codecr[] =
unsigned long codecr[] =
{
ASM_STW(stk, 1, -4),
ASM_ADDI(stk, 1, -16),
@@ -118,26 +118,26 @@ int cpu_post_test_srawi (void)
if (ret == 0)
{
cr = 0;
cpu_post_exec_21 (code, & cr, & res, test->op1);
cr = 0;
cpu_post_exec_21 (code, & cr, & res, test->op1);
ret = res == test->res && cr == 0 ? 0 : -1;
ret = res == test->res && cr == 0 ? 0 : -1;
if (ret != 0)
{
if (ret != 0)
{
post_log ("Error at srawi test %d !\n", i);
}
}
}
if (ret == 0)
{
cpu_post_exec_21 (codecr, & cr, & res, test->op1);
cpu_post_exec_21 (codecr, & cr, & res, test->op1);
ret = res == test->res &&
ret = res == test->res &&
(cr & 0xe0000000) == cpu_post_makecr (res) ? 0 : -1;
if (ret != 0)
{
if (ret != 0)
{
post_log ("Error at srawi test %d !\n", i);
}
}
@@ -145,7 +145,7 @@ int cpu_post_test_srawi (void)
}
if (flag)
enable_interrupts();
enable_interrupts();
return ret;
}

60
post/lib_ppc/three.c
View File

@@ -53,103 +53,103 @@ static struct cpu_post_three_s
} cpu_post_three_table[] =
{
{
OP_ADD,
OP_ADD,
100,
200,
300
},
{
OP_ADD,
OP_ADD,
100,
-200,
-100
},
{
OP_ADDC,
OP_ADDC,
100,
200,
300
},
{
OP_ADDC,
OP_ADDC,
100,
-200,
-100
},
{
OP_ADDE,
OP_ADDE,
100,
200,
300
},
{
OP_ADDE,
OP_ADDE,
100,
-200,
-100
},
{
OP_SUBF,
OP_SUBF,
100,
200,
100
},
{
OP_SUBF,
OP_SUBF,
300,
200,
-100
},
{
OP_SUBFC,
OP_SUBFC,
100,
200,
100
},
{
OP_SUBFC,
OP_SUBFC,
300,
200,
-100
},
{
OP_SUBFE,
OP_SUBFE,
100,
200,
200 + ~100
},
{
OP_SUBFE,
OP_SUBFE,
300,
200,
200 + ~300
},
{
OP_MULLW,
OP_MULLW,
200,
300,
200 * 300
},
{
OP_MULHW,
OP_MULHW,
0x10000000,
0x10000000,
0x1000000
},
{
OP_MULHWU,
OP_MULHWU,
0x80000000,
0x80000000,
0x40000000
},
{
OP_DIVW,
OP_DIVW,
-20,
5,
-4
},
{
OP_DIVWU,
OP_DIVWU,
0x8000,
0x200,
0x40
@@ -174,7 +174,7 @@ int cpu_post_test_three (void)
unsigned int reg1 = (reg + 1) % 32;
unsigned int reg2 = (reg + 2) % 32;
unsigned int stk = reg < 16 ? 31 : 15;
unsigned long code[] =
unsigned long code[] =
{
ASM_STW(stk, 1, -4),
ASM_ADDI(stk, 1, -24),
@@ -195,7 +195,7 @@ int cpu_post_test_three (void)
ASM_LWZ(stk, 1, -4),
ASM_BLR,
};
unsigned long codecr[] =
unsigned long codecr[] =
{
ASM_STW(stk, 1, -4),
ASM_ADDI(stk, 1, -24),
@@ -221,26 +221,26 @@ int cpu_post_test_three (void)
if (ret == 0)
{
cr = 0;
cpu_post_exec_22 (code, & cr, & res, test->op1, test->op2);
cr = 0;
cpu_post_exec_22 (code, & cr, & res, test->op1, test->op2);
ret = res == test->res && cr == 0 ? 0 : -1;
ret = res == test->res && cr == 0 ? 0 : -1;
if (ret != 0)
{
if (ret != 0)
{
post_log ("Error at three test %d !\n", i);
}
}
}
if (ret == 0)
{
cpu_post_exec_22 (codecr, & cr, & res, test->op1, test->op2);
cpu_post_exec_22 (codecr, & cr, & res, test->op1, test->op2);
ret = res == test->res &&
ret = res == test->res &&
(cr & 0xe0000000) == cpu_post_makecr (res) ? 0 : -1;
if (ret != 0)
{
if (ret != 0)
{
post_log ("Error at three test %d !\n", i);
}
}
@@ -248,7 +248,7 @@ int cpu_post_test_three (void)
}
if (flag)
enable_interrupts();
enable_interrupts();
return ret;
}

14
post/lib_ppc/threei.c
View File

@@ -51,25 +51,25 @@ static struct cpu_post_threei_s
} cpu_post_threei_table[] =
{
{
OP_ORI,
OP_ORI,
0x80000000,
0xffff,
0x8000ffff
},
{
OP_ORIS,
OP_ORIS,
0x00008000,
0xffff,
0xffff8000
},
{
OP_XORI,
OP_XORI,
0x8000ffff,
0xffff,
0x80000000
},
{
OP_XORIS,
OP_XORIS,
0x00008000,
0xffff,
0xffff8000
@@ -93,7 +93,7 @@ int cpu_post_test_threei (void)
unsigned int reg0 = (reg + 0) % 32;
unsigned int reg1 = (reg + 1) % 32;
unsigned int stk = reg < 16 ? 31 : 15;
unsigned long code[] =
unsigned long code[] =
{
ASM_STW(stk, 1, -4),
ASM_ADDI(stk, 1, -16),
@@ -113,7 +113,7 @@ int cpu_post_test_threei (void)
ulong res;
ulong cr;
cr = 0;
cr = 0;
cpu_post_exec_21 (code, & cr, & res, test->op1);
ret = res == test->res && cr == 0 ? 0 : -1;
@@ -126,7 +126,7 @@ int cpu_post_test_threei (void)
}
if (flag)
enable_interrupts();
enable_interrupts();
return ret;
}

50
post/lib_ppc/threex.c
View File

@@ -53,73 +53,73 @@ static struct cpu_post_threex_s
} cpu_post_threex_table[] =
{
{
OP_OR,
OP_OR,
0x1234,
0x5678,
0x1234 | 0x5678
},
{
OP_ORC,
OP_ORC,
0x1234,
0x5678,
0x1234 | ~0x5678
},
{
OP_XOR,
OP_XOR,
0x1234,
0x5678,
0x1234 ^ 0x5678
},
{
OP_NAND,
OP_NAND,
0x1234,
0x5678,
~(0x1234 & 0x5678)
},
{
OP_NOR,
OP_NOR,
0x1234,
0x5678,
~(0x1234 | 0x5678)
},
{
OP_EQV,
OP_EQV,
0x1234,
0x5678,
~(0x1234 ^ 0x5678)
},
{
OP_SLW,
OP_SLW,
0x80,
16,
0x800000
},
{
OP_SLW,
OP_SLW,
0x80,
32,
0
},
{
OP_SRW,
OP_SRW,
0x800000,
16,
0x80
},
{
OP_SRW,
OP_SRW,
0x800000,
32,
0
},
{
OP_SRAW,
OP_SRAW,
0x80000000,
3,
0xf0000000
},
{
OP_SRAW,
OP_SRAW,
0x8000,
3,
0x1000
@@ -144,7 +144,7 @@ int cpu_post_test_threex (void)
unsigned int reg1 = (reg + 1) % 32;
unsigned int reg2 = (reg + 2) % 32;
unsigned int stk = reg < 16 ? 31 : 15;
unsigned long code[] =
unsigned long code[] =
{
ASM_STW(stk, 1, -4),
ASM_ADDI(stk, 1, -24),
@@ -165,7 +165,7 @@ int cpu_post_test_threex (void)
ASM_LWZ(stk, 1, -4),
ASM_BLR,
};
unsigned long codecr[] =
unsigned long codecr[] =
{
ASM_STW(stk, 1, -4),
ASM_ADDI(stk, 1, -24),
@@ -191,26 +191,26 @@ int cpu_post_test_threex (void)
if (ret == 0)
{
cr = 0;
cpu_post_exec_22 (code, & cr, & res, test->op1, test->op2);
cr = 0;
cpu_post_exec_22 (code, & cr, & res, test->op1, test->op2);
ret = res == test->res && cr == 0 ? 0 : -1;
ret = res == test->res && cr == 0 ? 0 : -1;
if (ret != 0)
{
if (ret != 0)
{
post_log ("Error at threex test %d !\n", i);
}
}
}
if (ret == 0)
{
cpu_post_exec_22 (codecr, & cr, & res, test->op1, test->op2);
cpu_post_exec_22 (codecr, & cr, & res, test->op1, test->op2);
ret = res == test->res &&
ret = res == test->res &&
(cr & 0xe0000000) == cpu_post_makecr (res) ? 0 : -1;
if (ret != 0)
{
if (ret != 0)
{
post_log ("Error at threex test %d !\n", i);
}
}
@@ -218,7 +218,7 @@ int cpu_post_test_threex (void)
}
if (flag)
enable_interrupts();
enable_interrupts();
return ret;
}

38
post/lib_ppc/twox.c
View File

@@ -51,32 +51,32 @@ static struct cpu_post_twox_s
} cpu_post_twox_table[] =
{
{
OP_EXTSB,
OP_EXTSB,
3,
3
},
{
OP_EXTSB,
OP_EXTSB,
0xff,
-1
},
{
OP_EXTSH,
OP_EXTSH,
3,
3
},
{
OP_EXTSH,
OP_EXTSH,
0xff,
0xff
},
{
OP_EXTSH,
OP_EXTSH,
0xffff,
-1
},
{
OP_CNTLZW,
OP_CNTLZW,
0x000fffff,
12
},
@@ -99,7 +99,7 @@ int cpu_post_test_twox (void)
unsigned int reg0 = (reg + 0) % 32;
unsigned int reg1 = (reg + 1) % 32;
unsigned int stk = reg < 16 ? 31 : 15;
unsigned long code[] =
unsigned long code[] =
{
ASM_STW(stk, 1, -4),
ASM_ADDI(stk, 1, -16),
@@ -116,7 +116,7 @@ int cpu_post_test_twox (void)
ASM_LWZ(stk, 1, -4),
ASM_BLR,
};
unsigned long codecr[] =
unsigned long codecr[] =
{
ASM_STW(stk, 1, -4),
ASM_ADDI(stk, 1, -16),
@@ -138,26 +138,26 @@ int cpu_post_test_twox (void)
if (ret == 0)
{
cr = 0;
cpu_post_exec_21 (code, & cr, & res, test->op);
cr = 0;
cpu_post_exec_21 (code, & cr, & res, test->op);
ret = res == test->res && cr == 0 ? 0 : -1;
ret = res == test->res && cr == 0 ? 0 : -1;
if (ret != 0)
{
if (ret != 0)
{
post_log ("Error at twox test %d !\n", i);
}
}
}
if (ret == 0)
{
cpu_post_exec_21 (codecr, & cr, & res, test->op);
cpu_post_exec_21 (codecr, & cr, & res, test->op);
ret = res == test->res &&
ret = res == test->res &&
(cr & 0xe0000000) == cpu_post_makecr (res) ? 0 : -1;
if (ret != 0)
{
if (ret != 0)
{
post_log ("Error at twox test %d !\n", i);
}
}
@@ -165,7 +165,7 @@ int cpu_post_test_twox (void)
}
if (flag)
enable_interrupts();
enable_interrupts();
return ret;
}

2
post/rules.mk
View File

@@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk
COBJS := $(COBJS-y)
AOBJS := $(AOBJS-y)
SRCS := $(AOBJS:.o=.S) $(COBJS:.o=.c)
SRCS := $(AOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(AOBJS) $(COBJS))
LIB := $(obj)$(LIB)