ARM: Add support for IGEP COM AQUILA/CYGNUS
The IGEP COM AQUILA and CYGNUS are industrial processors modules with following highlights: o AM3352/AM3354 Texas Instruments processor o Cortex-A8 ARM CPU o 3.3 volts Inputs / Outputs use industrial o 256 MB DDR3 SDRAM / 128 Megabytes FLASH o MicroSD card reader on-board o Ethernet controller on-board o JTAG debug connector available o Designed for industrial range purposes Signed-off-by: Enric Balletbo i Serra <eballetbo@iseebcn.com>
This commit is contained in:
Enric Balletbo i Serra
committed by
Tom Rini
Tom Rini
parent
cc175e6353
commit
5f5c1d13d3
46
board/isee/igep0033/Makefile
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46
board/isee/igep0033/Makefile
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#
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# Makefile
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#
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# Copyright (C) 2013, ISEE 2007 SL - http://www.isee.biz/
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#
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# This program is free software; you can redistribute it and/or
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# modify it under the terms of the GNU General Public License as
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# published by the Free Software Foundation; either version 2 of
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# the License, or (at your option) any later version.
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#
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# This program is distributed "as is" WITHOUT ANY WARRANTY of any
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# kind, whether express or implied; without even the implied warranty
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# of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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include $(TOPDIR)/config.mk
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LIB = $(obj)lib$(BOARD).o
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ifdef CONFIG_SPL_BUILD
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COBJS := mux.o
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endif
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COBJS += board.o
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SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
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OBJS := $(addprefix $(obj),$(COBJS))
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SOBJS := $(addprefix $(obj),$(SOBJS))
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$(LIB): $(obj).depend $(OBJS) $(SOBJS)
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$(call cmd_link_o_target, $(OBJS) $(SOBJS))
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clean:
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rm -f $(SOBJS) $(OBJS)
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distclean: clean
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rm -f $(LIB) core *.bak $(obj).depend
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#########################################################################
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# defines $(obj).depend target
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include $(SRCTREE)/rules.mk
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sinclude $(obj).depend
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#########################################################################
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232
board/isee/igep0033/board.c
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232
board/isee/igep0033/board.c
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/*
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* Board functions for IGEP COM AQUILA/CYGNUS based boards
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*
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* Copyright (C) 2013, ISEE 2007 SL - http://www.isee.biz/
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <common.h>
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#include <errno.h>
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#include <spl.h>
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#include <asm/arch/cpu.h>
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#include <asm/arch/hardware.h>
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#include <asm/arch/omap.h>
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#include <asm/arch/ddr_defs.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/gpio.h>
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#include <asm/arch/mmc_host_def.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/io.h>
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#include <asm/emif.h>
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#include <asm/gpio.h>
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#include <i2c.h>
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#include <miiphy.h>
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#include <cpsw.h>
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#include "board.h"
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DECLARE_GLOBAL_DATA_PTR;
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static struct wd_timer *wdtimer = (struct wd_timer *)WDT_BASE;
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#ifdef CONFIG_SPL_BUILD
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static struct uart_sys *uart_base = (struct uart_sys *)DEFAULT_UART_BASE;
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#endif
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/* MII mode defines */
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#define RMII_MODE_ENABLE 0x4D
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static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
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/* UART Defines */
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#ifdef CONFIG_SPL_BUILD
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#define UART_RESET (0x1 << 1)
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#define UART_CLK_RUNNING_MASK 0x1
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#define UART_SMART_IDLE_EN (0x1 << 0x3)
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static void rtc32k_enable(void)
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{
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struct rtc_regs *rtc = (struct rtc_regs *)RTC_BASE;
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/*
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* Unlock the RTC's registers. For more details please see the
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* RTC_SS section of the TRM. In order to unlock we need to
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* write these specific values (keys) in this order.
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*/
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writel(0x83e70b13, &rtc->kick0r);
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writel(0x95a4f1e0, &rtc->kick1r);
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/* Enable the RTC 32K OSC by setting bits 3 and 6. */
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writel((1 << 3) | (1 << 6), &rtc->osc);
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}
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static const struct ddr_data ddr3_data = {
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.datardsratio0 = K4B2G1646EBIH9_RD_DQS,
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.datawdsratio0 = K4B2G1646EBIH9_WR_DQS,
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.datafwsratio0 = K4B2G1646EBIH9_PHY_FIFO_WE,
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.datawrsratio0 = K4B2G1646EBIH9_PHY_WR_DATA,
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.datadldiff0 = PHY_DLL_LOCK_DIFF,
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};
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static const struct cmd_control ddr3_cmd_ctrl_data = {
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.cmd0csratio = K4B2G1646EBIH9_RATIO,
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.cmd0dldiff = K4B2G1646EBIH9_DLL_LOCK_DIFF,
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.cmd0iclkout = K4B2G1646EBIH9_INVERT_CLKOUT,
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.cmd1csratio = K4B2G1646EBIH9_RATIO,
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.cmd1dldiff = K4B2G1646EBIH9_DLL_LOCK_DIFF,
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.cmd1iclkout = K4B2G1646EBIH9_INVERT_CLKOUT,
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.cmd2csratio = K4B2G1646EBIH9_RATIO,
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.cmd2dldiff = K4B2G1646EBIH9_DLL_LOCK_DIFF,
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.cmd2iclkout = K4B2G1646EBIH9_INVERT_CLKOUT,
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};
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static struct emif_regs ddr3_emif_reg_data = {
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.sdram_config = K4B2G1646EBIH9_EMIF_SDCFG,
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.ref_ctrl = K4B2G1646EBIH9_EMIF_SDREF,
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.sdram_tim1 = K4B2G1646EBIH9_EMIF_TIM1,
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.sdram_tim2 = K4B2G1646EBIH9_EMIF_TIM2,
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.sdram_tim3 = K4B2G1646EBIH9_EMIF_TIM3,
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.zq_config = K4B2G1646EBIH9_ZQ_CFG,
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.emif_ddr_phy_ctlr_1 = K4B2G1646EBIH9_EMIF_READ_LATENCY,
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};
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#endif
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/*
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* Early system init of muxing and clocks.
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*/
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void s_init(void)
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{
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/* WDT1 is already running when the bootloader gets control
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* Disable it to avoid "random" resets
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*/
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writel(0xAAAA, &wdtimer->wdtwspr);
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while (readl(&wdtimer->wdtwwps) != 0x0)
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;
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writel(0x5555, &wdtimer->wdtwspr);
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while (readl(&wdtimer->wdtwwps) != 0x0)
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;
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#ifdef CONFIG_SPL_BUILD
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/* Setup the PLLs and the clocks for the peripherals */
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pll_init();
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/* Enable RTC32K clock */
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rtc32k_enable();
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/* UART softreset */
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u32 regval;
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enable_uart0_pin_mux();
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regval = readl(&uart_base->uartsyscfg);
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regval |= UART_RESET;
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writel(regval, &uart_base->uartsyscfg);
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while ((readl(&uart_base->uartsyssts) &
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UART_CLK_RUNNING_MASK) != UART_CLK_RUNNING_MASK)
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;
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/* Disable smart idle */
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regval = readl(&uart_base->uartsyscfg);
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regval |= UART_SMART_IDLE_EN;
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writel(regval, &uart_base->uartsyscfg);
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gd = &gdata;
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preloader_console_init();
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/* Configure board pin mux */
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enable_board_pin_mux();
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config_ddr(303, K4B2G1646EBIH9_IOCTRL_VALUE, &ddr3_data,
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&ddr3_cmd_ctrl_data, &ddr3_emif_reg_data, 0);
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#endif
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}
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/*
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* Basic board specific setup. Pinmux has been handled already.
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*/
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int board_init(void)
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{
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gd->bd->bi_boot_params = PHYS_DRAM_1 + 0x100;
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gpmc_init();
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return 0;
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}
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#if defined(CONFIG_DRIVER_TI_CPSW)
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static void cpsw_control(int enabled)
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{
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/* VTP can be added here */
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return;
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}
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static struct cpsw_slave_data cpsw_slaves[] = {
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{
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.slave_reg_ofs = 0x208,
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.sliver_reg_ofs = 0xd80,
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.phy_id = 0,
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.phy_if = PHY_INTERFACE_MODE_RMII,
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},
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};
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static struct cpsw_platform_data cpsw_data = {
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.mdio_base = CPSW_MDIO_BASE,
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.cpsw_base = CPSW_BASE,
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.mdio_div = 0xff,
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.channels = 8,
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.cpdma_reg_ofs = 0x800,
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.slaves = 1,
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.slave_data = cpsw_slaves,
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.ale_reg_ofs = 0xd00,
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.ale_entries = 1024,
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.host_port_reg_ofs = 0x108,
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.hw_stats_reg_ofs = 0x900,
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.mac_control = (1 << 5),
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.control = cpsw_control,
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.host_port_num = 0,
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.version = CPSW_CTRL_VERSION_2,
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};
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int board_eth_init(bd_t *bis)
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{
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int rv, ret = 0;
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uint8_t mac_addr[6];
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uint32_t mac_hi, mac_lo;
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if (!eth_getenv_enetaddr("ethaddr", mac_addr)) {
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/* try reading mac address from efuse */
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mac_lo = readl(&cdev->macid0l);
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mac_hi = readl(&cdev->macid0h);
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mac_addr[0] = mac_hi & 0xFF;
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mac_addr[1] = (mac_hi & 0xFF00) >> 8;
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mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
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mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
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mac_addr[4] = mac_lo & 0xFF;
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mac_addr[5] = (mac_lo & 0xFF00) >> 8;
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if (is_valid_ether_addr(mac_addr))
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eth_setenv_enetaddr("ethaddr", mac_addr);
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}
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writel(RMII_MODE_ENABLE, &cdev->miisel);
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rv = cpsw_register(&cpsw_data);
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if (rv < 0)
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printf("Error %d registering CPSW switch\n", rv);
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else
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ret += rv;
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return ret;
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}
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#endif
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27
board/isee/igep0033/board.h
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27
board/isee/igep0033/board.h
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@@ -0,0 +1,27 @@
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/*
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* IGEP COM AQUILA/CYGNUS boards information header
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*
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* Copyright (C) 2013, ISEE 2007 SL - http://www.isee.biz/
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef _BOARD_H_
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#define _BOARD_H_
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/*
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* We must be able to enable uart0, for initial output. We then have a
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* main pinmux function that can be overridden to enable all other pinmux that
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* is required on the board.
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*/
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void enable_uart0_pin_mux(void);
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void enable_board_pin_mux(void);
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#endif
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89
board/isee/igep0033/mux.c
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89
board/isee/igep0033/mux.c
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@@ -0,0 +1,89 @@
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/*
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* Copyright (C) 2013, ISEE 2007 SL - http://www.isee.biz/
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation version 2.
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*
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* This program is distributed "as is" WITHOUT ANY WARRANTY of any
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* kind, whether express or implied; without even the implied warranty
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* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <common.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/arch/hardware.h>
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#include <asm/arch/mux.h>
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#include <asm/io.h>
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#include <i2c.h>
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#include "board.h"
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static struct module_pin_mux uart0_pin_mux[] = {
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{OFFSET(uart0_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* UART0_RXD */
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{OFFSET(uart0_txd), (MODE(0) | PULLUDEN)}, /* UART0_TXD */
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{-1},
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};
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static struct module_pin_mux mmc0_pin_mux[] = {
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{OFFSET(mmc0_dat3), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT3 */
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{OFFSET(mmc0_dat2), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT2 */
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{OFFSET(mmc0_dat1), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT1 */
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{OFFSET(mmc0_dat0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT0 */
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{OFFSET(mmc0_clk), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CLK */
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{OFFSET(mmc0_cmd), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CMD */
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{OFFSET(mcasp0_aclkx), (MODE(4) | RXACTIVE)}, /* MMC0_CD */
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{-1},
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};
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static struct module_pin_mux nand_pin_mux[] = {
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{OFFSET(gpmc_ad0), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD0 */
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{OFFSET(gpmc_ad1), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD1 */
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{OFFSET(gpmc_ad2), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD2 */
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{OFFSET(gpmc_ad3), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD3 */
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{OFFSET(gpmc_ad4), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD4 */
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{OFFSET(gpmc_ad5), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD5 */
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{OFFSET(gpmc_ad6), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD6 */
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{OFFSET(gpmc_ad7), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD7 */
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{OFFSET(gpmc_wait0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* NAND WAIT */
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{OFFSET(gpmc_wpn), (MODE(7) | PULLUP_EN | RXACTIVE)}, /* NAND_WPN */
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{OFFSET(gpmc_csn0), (MODE(0) | PULLUDEN)}, /* NAND_CS0 */
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{OFFSET(gpmc_advn_ale), (MODE(0) | PULLUDEN)}, /* NAND_ADV_ALE */
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{OFFSET(gpmc_oen_ren), (MODE(0) | PULLUDEN)}, /* NAND_OE */
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{OFFSET(gpmc_wen), (MODE(0) | PULLUDEN)}, /* NAND_WEN */
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{OFFSET(gpmc_be0n_cle), (MODE(0) | PULLUDEN)}, /* NAND_BE_CLE */
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{-1},
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};
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static struct module_pin_mux rmii1_pin_mux[] = {
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{OFFSET(mii1_txen), MODE(1)}, /* RMII1_TXEN */
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{OFFSET(mii1_rxerr), MODE(1) | RXACTIVE}, /* RMII1_RXERR */
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{OFFSET(mii1_crs), MODE(1) | RXACTIVE}, /* RMII1_CRS_DV */
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{OFFSET(mii1_rxd0), MODE(1) | RXACTIVE}, /* RMII1_RXD0 */
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{OFFSET(mii1_rxd1), MODE(1) | RXACTIVE}, /* RMII1_RXD1 */
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{OFFSET(mii1_txd0), MODE(1)}, /* RMII1_TXD0 */
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{OFFSET(mii1_txd1), MODE(1)}, /* RMII1_TXD1 */
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{OFFSET(rmii1_refclk), MODE(0) | RXACTIVE}, /* RMII1_REF_CLK */
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{OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN}, /* MDIO_DATA */
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{OFFSET(mdio_clk), MODE(0) | PULLUP_EN}, /* MDIO_CLK */
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{-1},
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};
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void enable_uart0_pin_mux(void)
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{
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configure_module_pin_mux(uart0_pin_mux);
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}
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/*
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* Do board-specific muxes.
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*/
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void enable_board_pin_mux(void)
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{
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/* NAND Flash */
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configure_module_pin_mux(nand_pin_mux);
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/* SD Card */
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configure_module_pin_mux(mmc0_pin_mux);
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/* Ethernet pinmux. */
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configure_module_pin_mux(rmii1_pin_mux);
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}
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