arm: socfpga: config: Move SPL GD and malloc to RAM

Now that the SPL structure is organised such that it matches the
U-Boot's SPL design, it is possible to use the option of relocating
GD to RAM. And since we have GD in RAM, move malloc area to RAM as
well. We point the malloc base pointer 1 MiB past U-Boot's load
address. We use simple malloc for SPL because it is 3kiB smaller
in terms of code size than regular malloc which was used thus far.

Signed-off-by: Marek Vasut <marex@denx.de>

configs/socfpga_cyclone5_defconfig

@@ -17,3 +17,6 @@ CONFIG_SPL_SIMPLE_BUS=y
 CONFIG_DM_SPI=y
 CONFIG_DM_SPI_FLASH=y
 CONFIG_SPL_SPI_SUPPORT=y
+CONFIG_SPL_STACK_R=y
+CONFIG_SPL_STACK_R_ADDR=0x00800000
+CONFIG_SYS_MALLOC_F_LEN=0x2000