Merge branch 'master' of git://git.denx.de/u-boot-fsl-qoriq

This commit is contained in:
Tom Rini
2014-11-25 16:51:47 -05:00
19 changed files with 335 additions and 71 deletions

View File

@@ -27,7 +27,10 @@
#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x011c0500)
#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x011d0500)
#define CONFIG_SYS_DCU_ADDR (CONFIG_SYS_IMMR + 0x01ce0000)
#define CONFIG_SYS_LS102XA_USB1_ADDR \
(CONFIG_SYS_IMMR + CONFIG_SYS_LS102XA_USB1_OFFSET)
#define CONFIG_SYS_LS102XA_USB1_OFFSET 0x07600000
#define CONFIG_SYS_TSEC1_OFFSET 0x01d10000
#define CONFIG_SYS_TSEC2_OFFSET 0x01d50000
#define CONFIG_SYS_TSEC3_OFFSET 0x01d90000
@@ -72,6 +75,10 @@
#define DCU_LAYER_MAX_NUM 16
#define QE_MURAM_SIZE 0x6000UL
#define MAX_QE_RISC 1
#define QE_NUM_OF_SNUM 28
#define CONFIG_SYS_FSL_SRDS_1
#ifdef CONFIG_LS102XA
@@ -80,6 +87,7 @@
#define CONFIG_NUM_DDR_CONTROLLERS 1
#define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_5_0
#define CONFIG_SYS_FSL_SEC_COMPAT 5
#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
#else
#error SoC not defined
#endif

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@@ -95,8 +95,6 @@ struct ccsr_gur {
u32 sdhcpcr;
};
#define SCFG_SCFGREVCR_REV 0xffffffff
#define SCFG_SCFGREVCR_NOREV 0
#define SCFG_ETSECDMAMCR_LE_BD_FR 0xf8001a0f
#define SCFG_ETSECCMCR_GE2_CLK125 0x04000000
#define SCFG_PIXCLKCR_PXCKEN 0x80000000
@@ -182,7 +180,7 @@ struct ccsr_scfg {
u32 etsecmcr;
u32 sdhciovserlcr;
u32 resv14[61];
u32 sparecr;
u32 sparecr[8];
};
/* Clocking */
@@ -448,6 +446,7 @@ struct ccsr_ddr {
#define CCI400_CTRLORD_TERM_BARRIER 0x00000008
#define CCI400_CTRLORD_EN_BARRIER 0
#define CCI400_SHAORD_NON_SHAREABLE 0x00000002
/* CCI-400 registers */
struct ccsr_cci400 {

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@@ -17,6 +17,14 @@ struct arch_global_data {
#if defined(CONFIG_FSL_ESDHC)
u32 sdhc_clk;
#endif
#if defined(CONFIG_U_QE)
u32 qe_clk;
u32 brg_clk;
uint mp_alloc_base;
uint mp_alloc_top;
#endif /* CONFIG_U_QE */
#ifdef CONFIG_AT91FAMILY
/* "static data" needed by at91's clock.c */
unsigned long cpu_clk_rate_hz;