Merge branch 'master' of git://git.denx.de/u-boot-fsl-qoriq
This commit is contained in:
@@ -27,7 +27,10 @@
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#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x011c0500)
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#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x011d0500)
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#define CONFIG_SYS_DCU_ADDR (CONFIG_SYS_IMMR + 0x01ce0000)
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#define CONFIG_SYS_LS102XA_USB1_ADDR \
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(CONFIG_SYS_IMMR + CONFIG_SYS_LS102XA_USB1_OFFSET)
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#define CONFIG_SYS_LS102XA_USB1_OFFSET 0x07600000
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#define CONFIG_SYS_TSEC1_OFFSET 0x01d10000
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#define CONFIG_SYS_TSEC2_OFFSET 0x01d50000
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#define CONFIG_SYS_TSEC3_OFFSET 0x01d90000
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@@ -72,6 +75,10 @@
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#define DCU_LAYER_MAX_NUM 16
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#define QE_MURAM_SIZE 0x6000UL
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#define MAX_QE_RISC 1
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#define QE_NUM_OF_SNUM 28
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#define CONFIG_SYS_FSL_SRDS_1
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#ifdef CONFIG_LS102XA
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@@ -80,6 +87,7 @@
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#define CONFIG_NUM_DDR_CONTROLLERS 1
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#define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_5_0
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#define CONFIG_SYS_FSL_SEC_COMPAT 5
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#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
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#else
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#error SoC not defined
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#endif
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@@ -95,8 +95,6 @@ struct ccsr_gur {
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u32 sdhcpcr;
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};
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#define SCFG_SCFGREVCR_REV 0xffffffff
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#define SCFG_SCFGREVCR_NOREV 0
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#define SCFG_ETSECDMAMCR_LE_BD_FR 0xf8001a0f
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#define SCFG_ETSECCMCR_GE2_CLK125 0x04000000
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#define SCFG_PIXCLKCR_PXCKEN 0x80000000
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@@ -182,7 +180,7 @@ struct ccsr_scfg {
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u32 etsecmcr;
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u32 sdhciovserlcr;
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u32 resv14[61];
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u32 sparecr;
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u32 sparecr[8];
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};
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/* Clocking */
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@@ -448,6 +446,7 @@ struct ccsr_ddr {
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#define CCI400_CTRLORD_TERM_BARRIER 0x00000008
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#define CCI400_CTRLORD_EN_BARRIER 0
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#define CCI400_SHAORD_NON_SHAREABLE 0x00000002
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/* CCI-400 registers */
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struct ccsr_cci400 {
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@@ -17,6 +17,14 @@ struct arch_global_data {
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#if defined(CONFIG_FSL_ESDHC)
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u32 sdhc_clk;
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#endif
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#if defined(CONFIG_U_QE)
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u32 qe_clk;
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u32 brg_clk;
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uint mp_alloc_base;
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uint mp_alloc_top;
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#endif /* CONFIG_U_QE */
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#ifdef CONFIG_AT91FAMILY
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/* "static data" needed by at91's clock.c */
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unsigned long cpu_clk_rate_hz;
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