From 90aea84d9c867bc3487847a0f41460ad80d39a65 Mon Sep 17 00:00:00 2001 From: Peter Chubb Date: Tue, 30 Aug 2016 09:58:15 +1000 Subject: [PATCH] rtl8169: fix cache misalignment message on transmit. The call to flush cache on the transmit buffer was misplaced (for very short packets) and asked to flush less than a cacheline. Move the flush cache call to after a short packet has been padded to minimum length (so the padding is flushed too), and round the size up to a cacheline. Signed-off-by: Peter Chubb --- drivers/net/rtl8169.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/net/rtl8169.c b/drivers/net/rtl8169.c index 1cc0b40935..a3f4423a20 100644 --- a/drivers/net/rtl8169.c +++ b/drivers/net/rtl8169.c @@ -629,11 +629,12 @@ static int rtl_send_common(pci_dev_t dev, unsigned long dev_iobase, /* point to the current txb incase multiple tx_rings are used */ ptxb = tpc->Tx_skbuff[entry * MAX_ETH_FRAME_SIZE]; memcpy(ptxb, (char *)packet, (int)length); - rtl_flush_buffer(ptxb, length); while (len < ETH_ZLEN) ptxb[len++] = '\0'; + rtl_flush_buffer(ptxb, ALIGN(len, RTL8169_ALIGN)); + tpc->TxDescArray[entry].buf_Haddr = 0; #ifdef CONFIG_DM_ETH tpc->TxDescArray[entry].buf_addr = cpu_to_le32(