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ppc4xx: 4xx_pcie: More general cleanup and 405EX PCIe support added

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Signed-off-by: Stefan Roese <sr@denx.de>
This commit is contained in:
Stefan Roese
2007-10-05 09:18:23 +02:00
parent 4dbee8a90d
commit 97923770cb
4 changed files with 79 additions and 51 deletions
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31
include/asm-ppc/4xx_pcie.h
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@@ -16,14 +16,29 @@
#define DCRN_SDR0_CFGDATA 0x00f
#if defined(CONFIG_440SPE)
#define CFG_PCIE_NR_PORTS 3
#define CFG_PCIE_ADDR_HIGH 0x0000000d
#define DCRN_PCIE0_BASE 0x100
#define DCRN_PCIE1_BASE 0x120
#define DCRN_PCIE2_BASE 0x140
#define PCIE0_SDR 0x300
#define PCIE1_SDR 0x340
#define PCIE2_SDR 0x370
#endif
#if defined(CONFIG_405EX)
#define CFG_PCIE_NR_PORTS 2
#define CFG_PCIE_ADDR_HIGH 0x00000000
#define DCRN_PCIE0_BASE 0x040
#define DCRN_PCIE1_BASE 0x060
#define PCIE0_SDR 0x400
#define PCIE1_SDR 0x440
#endif
#define PCIE0 DCRN_PCIE0_BASE
@@ -53,17 +68,6 @@
#define PESDR0_PLLLCT2 0x03a1
#define PESDR0_PLLLCT3 0x03a2
#if defined(CONFIG_440SPE)
#define PCIE0_SDR 0x300
#define PCIE1_SDR 0x340
#define PCIE2_SDR 0x370
#endif
#if defined(CONFIG_405EX)
#define PCIE0_SDR 0x400
#define PCIE1_SDR 0x440
#endif
/* common regs, at least for 405EX and 440SPe */
#define SDRN_PESDR_UTLSET1(n) (sdr_base(n) + 0x00)
#define SDRN_PESDR_UTLSET2(n) (sdr_base(n) + 0x01)
@@ -237,6 +241,9 @@
#define GPL_DMER_MASK_DISA 0x02000000
#define U64_TO_U32_LOW(val) ((u32)((val) & 0x00000000ffffffffULL))
#define U64_TO_U32_HIGH(val) ((u32)((val) >> 32))
int ppc4xx_init_pcie(void);
int ppc4xx_init_pcie_rootport(int port);
int ppc4xx_init_pcie_endport(int port);
@@ -260,7 +267,7 @@ static inline u32 sdr_base(int port)
return PCIE0_SDR;
case 1:
return PCIE1_SDR;
#if defined(PCIE2_SDR)
#if CFG_PCIE_NR_PORTS > 2
case 2:
return PCIE2_SDR;
#endif

3
include/configs/katmai.h
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@@ -72,6 +72,9 @@
#define CFG_PCIE1_XCFGBASE 0xc3001000
#define CFG_PCIE2_XCFGBASE 0xc3002000
/* base address of inbound PCIe window */
#define CFG_PCIE_INBOUND_BASE 0x0000000400000000ULL
/* System RAM mapped to PCI space */
#define CONFIG_PCI_SYS_MEM_BUS CFG_SDRAM_BASE
#define CONFIG_PCI_SYS_MEM_PHYS CFG_SDRAM_BASE

3
include/configs/yucca.h
View File

@@ -74,6 +74,9 @@
#define CFG_PCIE1_XCFGBASE 0xc3001000
#define CFG_PCIE2_XCFGBASE 0xc3002000
/* base address of inbound PCIe window */
#define CFG_PCIE_INBOUND_BASE 0x0000000400000000ULL
/* System RAM mapped to PCI space */
#define CONFIG_PCI_SYS_MEM_BUS CFG_SDRAM_BASE
#define CONFIG_PCI_SYS_MEM_PHYS CFG_SDRAM_BASE