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Merge branch 'mpc86xx'

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This commit is contained in:
Jon Loeliger
2006-05-09 08:33:11 -05:00
parent 4af099bda9 18b6c8cd8a
commit a67255363a
35 changed files with 8298 additions and 19 deletions
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1362
include/asm-ppc/immap_86xx.h Normal file
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File diff suppressed because it is too large Load Diff

15
include/asm-ppc/mmu.h
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@@ -434,19 +434,28 @@ extern int write_bat(ppc_bat_t bat, unsigned long upper, unsigned long lower);
#define BOOKE_PAGESZ_1GB 10
#define BOOKE_PAGESZ_4GB 11
#if defined(CONFIG_MPC86xx)
#define LAWBAR_BASE_ADDR 0x00FFFFFF
#define LAWAR_TRGT_IF 0x01F00000
#else
#define LAWBAR_BASE_ADDR 0x000FFFFF
#define LAWAR_EN 0x80000000
#define LAWAR_TRGT_IF 0x00F00000
#endif
#define LAWAR_EN 0x80000000
#define LAWAR_SIZE 0x0000003F
#define LAWAR_TRGT_IF_PCI 0x00000000
#define LAWAR_TRGT_IF_PCI1 0x00000000
#define LAWAR_TRGT_IF_PCIX 0x00000000
#define LAWAR_TRGT_IF_PCI2 0x00100000
#define LAWAR_TRGT_IF_HT 0x00200000
#define LAWAR_TRGT_IF_LBC 0x00400000
#define LAWAR_TRGT_IF_CCSR 0x00800000
#define LAWAR_TRGT_IF_DDR_INTERLEAVED 0x00B00000
#define LAWAR_TRGT_IF_RIO 0x00c00000
#define LAWAR_TRGT_IF_DDR 0x00f00000
#define LAWAR_TRGT_IF_DDR1 0x00f00000
#define LAWAR_TRGT_IF_DDR2 0x01600000
#define LAWAR_SIZE_BASE 0xa
#define LAWAR_SIZE_4K (LAWAR_SIZE_BASE+1)
@@ -469,5 +478,9 @@ extern int write_bat(ppc_bat_t bat, unsigned long upper, unsigned long lower);
#define LAWAR_SIZE_512M (LAWAR_SIZE_BASE+18)
#define LAWAR_SIZE_1G (LAWAR_SIZE_BASE+19)
#define LAWAR_SIZE_2G (LAWAR_SIZE_BASE+20)
#define LAWAR_SIZE_4G (LAWAR_SIZE_BASE+21)
#define LAWAR_SIZE_8G (LAWAR_SIZE_BASE+22)
#define LAWAR_SIZE_16G (LAWAR_SIZE_BASE+23)
#define LAWAR_SIZE_32G (LAWAR_SIZE_BASE+24)
#endif /* _PPC_MMU_H_ */

18
include/asm-ppc/processor.h
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@@ -264,6 +264,7 @@
#define SPRN_ICTC 0x3FB /* Instruction Cache Throttling Control Reg */
#define SPRN_IMISS 0x3D4 /* Instruction TLB Miss Register */
#define SPRN_IMMR 0x27E /* Internal Memory Map Register */
#define SPRN_LDSTCR 0x3F8 /* Load/Store Control Register */
#define SPRN_L2CR 0x3F9 /* Level 2 Cache Control Regsiter */
#define SPRN_LR 0x008 /* Link Register */
#define SPRN_MBAR 0x137 /* System memory base address */
@@ -443,6 +444,11 @@
#define SPRN_MCSR 0x23c /* Machine Check Syndrome register */
#define ESR_ST 0x00800000 /* Store Operation */
#if defined(CONFIG_MPC86xx)
#define SPRN_MSSCRO 0x3f6
#endif
/* Short-hand versions for a number of the above SPRNs */
#define CTR SPRN_CTR /* Counter Register */
@@ -501,10 +507,14 @@
#define ICMP SPRN_ICMP /* Instruction TLB Compare Register */
#define IMISS SPRN_IMISS /* Instruction TLB Miss Register */
#define IMMR SPRN_IMMR /* PPC 860/821 Internal Memory Map Register */
#define LDSTCR SPRN_LDSTCR /* Load/Store Control Register */
#define L2CR SPRN_L2CR /* PPC 750 L2 control register */
#define LR SPRN_LR
#define MBAR SPRN_MBAR /* System memory base address */
#if defined(CONFIG_E500)
#if defined(CONFIG_MPC86xx)
#define MSSCR0 SPRN_MSSCRO
#endif
#if defined(CONFIG_E500) || defined(CONFIG_MPC86xx)
#define PIR SPRN_PIR
#endif
#define SVR SPRN_SVR /* System-On-Chip Version Register */
@@ -538,7 +548,7 @@
#define CSRR0 SPRN_CSRR0
#define CSRR1 SPRN_CSRR1
#define IVPR SPRN_IVPR
#define USPRG0 SPRN_USPRG0
#define USPRG0 SPRN_USPRG
#define SPRG4R SPRN_SPRG4R
#define SPRG5R SPRN_SPRG5R
#define SPRG6R SPRN_SPRG6R
@@ -755,6 +765,8 @@
#define PVR_85xx_REV1 (PVR_85xx | 0x0010)
#define PVR_85xx_REV2 (PVR_85xx | 0x0020)
#define PVR_86xx 0x80040000
#define PVR_86xx_REV1 (PVR_86xx | 0x0010)
/*
* For the 8xx processors, all of them report the same PVR family for
@@ -808,6 +820,8 @@
#define SVR_8548 0x8031
#define SVR_8548_E 0x8039
#define SVR_8641 0x8090
#define SVR_8641D 0x8091
/* I am just adding a single entry for 8260 boards. I think we may be
* able to combine mbx, fads, rpxlite, bseip, and classic into a single

2
include/asm-ppc/u-boot.h
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@@ -45,7 +45,7 @@ typedef struct bd_info {
unsigned long bi_sramstart; /* start of SRAM memory */
unsigned long bi_sramsize; /* size of SRAM memory */
#if defined(CONFIG_5xx) || defined(CONFIG_8xx) || defined(CONFIG_8260) \
|| defined(CONFIG_E500)
|| defined(CONFIG_E500) || defined(CONFIG_MPC86xx)
unsigned long bi_immr_base; /* base of IMMR register */
#endif
#if defined(CONFIG_MPC5xxx)