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Fix bug in [id]cache_status commands for MPC85xx processors;

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should look at LSB of L1CSRn registers to determine if L1 cache is
enabled, not the MSB.
Patch by Murray Jensen, 19 Jul 2005
This commit is contained in:
Wolfgang Denk
2006-03-13 00:46:05 +01:00
parent f07217c9e2
commit b38dbd4622
2 changed files with 7 additions and 2 deletions
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4
cpu/mpc85xx/start.S
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@@ -715,7 +715,7 @@ icache_disable:
.globl icache_status
icache_status:
mfspr r3,L1CSR1
srwi r3, r3, 31 /* >>31 => select bit 0 */
andi. r3,r3,1
blr
.globl dcache_enable
@@ -748,7 +748,7 @@ dcache_disable:
.globl dcache_status
dcache_status:
mfspr r3,L1CSR0
srwi r3, r3, 31 /* >>31 => select bit 0 */
andi. r3,r3,1
blr
.globl get_pir