Merge branch 'master' of /home/wd/git/u-boot/custodians
This commit is contained in:
Wolfgang Denk
@@ -89,6 +89,7 @@
|
||||
#define AT91SAM9_PMC_MDIV_1 (0 << 8) /* [SAM9,CAP9 only] */
|
||||
#define AT91SAM9_PMC_MDIV_2 (1 << 8)
|
||||
#define AT91SAM9_PMC_MDIV_4 (2 << 8)
|
||||
#define AT91SAM9_PMC_MDIV_3 (3 << 8) /* [some SAM9 only] */
|
||||
#define AT91SAM9_PMC_MDIV_6 (3 << 8)
|
||||
#define AT91_PMC_PDIV (1 << 12) /* Processor Clock Division [some SAM9 only] */
|
||||
#define AT91_PMC_PDIV_1 (0 << 12)
|
||||
|
||||
@@ -21,6 +21,8 @@
|
||||
#include <asm/arch/at91sam9rl_matrix.h>
|
||||
#elif defined(CONFIG_AT91CAP9)
|
||||
#include <asm/arch/at91cap9_matrix.h>
|
||||
#elif defined(CONFIG_AT91SAM9G45) || defined(CONFIG_AT91SAM9M10G45)
|
||||
#include <asm/arch/at91sam9g45_matrix.h>
|
||||
#else
|
||||
#error "Unsupported AT91SAM9/CAP9 processor"
|
||||
#endif
|
||||
|
||||
139
include/asm-arm/arch-at91/at91sam9g45.h
Normal file
139
include/asm-arm/arch-at91/at91sam9g45.h
Normal file
@@ -0,0 +1,139 @@
|
||||
/*
|
||||
* Chip-specific header file for the AT91SAM9M1x family
|
||||
*
|
||||
* Copyright (C) 2008 Atmel Corporation.
|
||||
*
|
||||
* Common definitions.
|
||||
* Based on AT91SAM9G45 preliminary datasheet.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*/
|
||||
|
||||
#ifndef AT91SAM9G45_H
|
||||
#define AT91SAM9G45_H
|
||||
|
||||
/*
|
||||
* Peripheral identifiers/interrupts.
|
||||
*/
|
||||
#define AT91_ID_FIQ 0 /* Advanced Interrupt Controller (FIQ) */
|
||||
#define AT91_ID_SYS 1 /* System Controller Interrupt */
|
||||
#define AT91SAM9G45_ID_PIOA 2 /* Parallel I/O Controller A */
|
||||
#define AT91SAM9G45_ID_PIOB 3 /* Parallel I/O Controller B */
|
||||
#define AT91SAM9G45_ID_PIOC 4 /* Parallel I/O Controller C */
|
||||
#define AT91SAM9G45_ID_PIODE 5 /* Parallel I/O Controller D and E */
|
||||
#define AT91SAM9G45_ID_TRNG 6 /* True Random Number Generator */
|
||||
#define AT91SAM9G45_ID_US0 7 /* USART 0 */
|
||||
#define AT91SAM9G45_ID_US1 8 /* USART 1 */
|
||||
#define AT91SAM9G45_ID_US2 9 /* USART 2 */
|
||||
#define AT91SAM9G45_ID_US3 10 /* USART 3 */
|
||||
#define AT91SAM9G45_ID_MCI0 11 /* High Speed Multimedia Card Interface 0 */
|
||||
#define AT91SAM9G45_ID_TWI0 12 /* Two-Wire Interface 0 */
|
||||
#define AT91SAM9G45_ID_TWI1 13 /* Two-Wire Interface 1 */
|
||||
#define AT91SAM9G45_ID_SPI0 14 /* Serial Peripheral Interface 0 */
|
||||
#define AT91SAM9G45_ID_SPI1 15 /* Serial Peripheral Interface 1 */
|
||||
#define AT91SAM9G45_ID_SSC0 16 /* Synchronous Serial Controller 0 */
|
||||
#define AT91SAM9G45_ID_SSC1 17 /* Synchronous Serial Controller 1 */
|
||||
#define AT91SAM9G45_ID_TCB 18 /* Timer Counter 0, 1, 2, 3, 4 and 5 */
|
||||
#define AT91SAM9G45_ID_PWMC 19 /* Pulse Width Modulation Controller */
|
||||
#define AT91SAM9G45_ID_TSC 20 /* Touch Screen ADC Controller */
|
||||
#define AT91SAM9G45_ID_DMA 21 /* DMA Controller */
|
||||
#define AT91SAM9G45_ID_UHPHS 22 /* USB Host High Speed */
|
||||
#define AT91SAM9G45_ID_LCDC 23 /* LCD Controller */
|
||||
#define AT91SAM9G45_ID_AC97C 24 /* AC97 Controller */
|
||||
#define AT91SAM9G45_ID_EMAC 25 /* Ethernet MAC */
|
||||
#define AT91SAM9G45_ID_ISI 26 /* Image Sensor Interface */
|
||||
#define AT91SAM9G45_ID_UDPHS 27 /* USB Device High Speed */
|
||||
#define AT91SAM9G45_ID_AESTDESSHA 28 /* AES + T-DES + SHA */
|
||||
#define AT91SAM9G45_ID_MCI1 29 /* High Speed Multimedia Card Interface 1 */
|
||||
#define AT91SAM9G45_ID_VDEC 30 /* Video Decoder */
|
||||
#define AT91SAM9G45_ID_IRQ0 31 /* Advanced Interrupt Controller */
|
||||
|
||||
/*
|
||||
* User Peripheral physical base addresses.
|
||||
*/
|
||||
#define AT91SAM9G45_BASE_UDPHS 0xfff78000
|
||||
#define AT91SAM9G45_BASE_TC0 0xfff7c000
|
||||
#define AT91SAM9G45_BASE_TC1 0xfff7c040
|
||||
#define AT91SAM9G45_BASE_TC2 0xfff7c080
|
||||
#define AT91SAM9G45_BASE_MCI0 0xfff80000
|
||||
#define AT91SAM9G45_BASE_TWI0 0xfff84000
|
||||
#define AT91SAM9G45_BASE_TWI1 0xfff88000
|
||||
#define AT91SAM9G45_BASE_US0 0xfff8c000
|
||||
#define AT91SAM9G45_BASE_US1 0xfff90000
|
||||
#define AT91SAM9G45_BASE_US2 0xfff94000
|
||||
#define AT91SAM9G45_BASE_US3 0xfff98000
|
||||
#define AT91SAM9G45_BASE_SSC0 0xfff9c000
|
||||
#define AT91SAM9G45_BASE_SSC1 0xfffa0000
|
||||
#define AT91SAM9G45_BASE_SPI0 0xfffa4000
|
||||
#define AT91SAM9G45_BASE_SPI1 0xfffa8000
|
||||
#define AT91SAM9G45_BASE_AC97C 0xfffac000
|
||||
#define AT91SAM9G45_BASE_TSC 0xfffb0000
|
||||
#define AT91SAM9G45_BASE_ISI 0xfffb4000
|
||||
#define AT91SAM9G45_BASE_PWMC 0xfffb8000
|
||||
#define AT91SAM9G45_BASE_EMAC 0xfffbc000
|
||||
#define AT91SAM9G45_BASE_AES 0xfffc0000
|
||||
#define AT91SAM9G45_BASE_TDES 0xfffc4000
|
||||
#define AT91SAM9G45_BASE_SHA 0xfffc8000
|
||||
#define AT91SAM9G45_BASE_TRNG 0xfffcc000
|
||||
#define AT91SAM9G45_BASE_MCI1 0xfffd0000
|
||||
#define AT91SAM9G45_BASE_TC3 0xfffd4000
|
||||
#define AT91SAM9G45_BASE_TC4 0xfffd4040
|
||||
#define AT91SAM9G45_BASE_TC5 0xfffd4080
|
||||
#define AT91_BASE_SYS 0xffffe200
|
||||
|
||||
/*
|
||||
* System Peripherals (offset from AT91_BASE_SYS)
|
||||
*/
|
||||
#define AT91_ECC (0xffffe200 - AT91_BASE_SYS)
|
||||
#define AT91_DDRSDRC1 (0xffffe400 - AT91_BASE_SYS)
|
||||
#define AT91_DDRSDRC0 (0xffffe600 - AT91_BASE_SYS)
|
||||
#define AT91_SMC (0xffffe800 - AT91_BASE_SYS)
|
||||
#define AT91_MATRIX (0xffffea00 - AT91_BASE_SYS)
|
||||
#define AT91_DMA (0xffffec00 - AT91_BASE_SYS)
|
||||
#define AT91_DBGU (0xffffee00 - AT91_BASE_SYS)
|
||||
#define AT91_AIC (0xfffff000 - AT91_BASE_SYS)
|
||||
#define AT91_PIOA (0xfffff200 - AT91_BASE_SYS)
|
||||
#define AT91_PIOB (0xfffff400 - AT91_BASE_SYS)
|
||||
#define AT91_PIOC (0xfffff600 - AT91_BASE_SYS)
|
||||
#define AT91_PIOD (0xfffff800 - AT91_BASE_SYS)
|
||||
#define AT91_PIOE (0xfffffa00 - AT91_BASE_SYS)
|
||||
#define AT91_PMC (0xfffffc00 - AT91_BASE_SYS)
|
||||
#define AT91_RSTC (0xfffffd00 - AT91_BASE_SYS)
|
||||
#define AT91_SHDWC (0xfffffd10 - AT91_BASE_SYS)
|
||||
#define AT91_RTT (0xfffffd20 - AT91_BASE_SYS)
|
||||
#define AT91_PIT (0xfffffd30 - AT91_BASE_SYS)
|
||||
#define AT91_WDT (0xfffffd40 - AT91_BASE_SYS)
|
||||
#define AT91_GPBR (0xfffffd60 - AT91_BASE_SYS)
|
||||
#define AT91_RTC (0xfffffdb0 - AT91_BASE_SYS)
|
||||
|
||||
#define AT91_USART0 AT91SAM9G45_BASE_US0
|
||||
#define AT91_USART1 AT91SAM9G45_BASE_US1
|
||||
#define AT91_USART2 AT91SAM9G45_BASE_US2
|
||||
#define AT91_USART3 AT91SAM9G45_BASE_US3
|
||||
|
||||
/*
|
||||
* Internal Memory.
|
||||
*/
|
||||
#define AT91SAM9G45_SRAM_BASE 0x00300000 /* Internal SRAM base address */
|
||||
#define AT91SAM9G45_SRAM_SIZE SZ_64K /* Internal SRAM size (64Kb) */
|
||||
|
||||
#define AT91SAM9G45_ROM_BASE 0x00400000 /* Internal ROM base address */
|
||||
#define AT91SAM9G45_ROM_SIZE SZ_64K /* Internal ROM size (64Kb) */
|
||||
|
||||
#define AT91SAM9G45_LCDC_BASE 0x00500000 /* LCD Controller */
|
||||
#define AT91SAM9G45_UDPHS_FIFO 0x00600000 /* USB Device HS controller */
|
||||
#define AT91SAM9G45_HCI_BASE 0x00700000 /* USB Host controller (OHCI) */
|
||||
#define AT91SAM9G45_EHCI_BASE 0x00800000 /* USB Host controller (EHCI) */
|
||||
#define AT91SAM9G45_VDEC_BASE 0x00900000 /* Video Decoder Controller */
|
||||
|
||||
#define CONFIG_DRAM_BASE AT91_CHIPSELECT_6
|
||||
|
||||
/*
|
||||
* Cpu Name
|
||||
*/
|
||||
#define AT91_CPU_NAME "AT91SAM9G45"
|
||||
|
||||
#endif
|
||||
153
include/asm-arm/arch-at91/at91sam9g45_matrix.h
Normal file
153
include/asm-arm/arch-at91/at91sam9g45_matrix.h
Normal file
@@ -0,0 +1,153 @@
|
||||
/*
|
||||
* Matrix-centric header file for the AT91SAM9M1x family
|
||||
*
|
||||
* Copyright (C) 2008 Atmel Corporation.
|
||||
*
|
||||
* Memory Controllers (MATRIX, EBI) - System peripherals registers.
|
||||
* Based on AT91SAM9G45 preliminary datasheet.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*/
|
||||
|
||||
#ifndef AT91SAM9G45_MATRIX_H
|
||||
#define AT91SAM9G45_MATRIX_H
|
||||
|
||||
#define AT91_MATRIX_MCFG0 (AT91_MATRIX + 0x00) /* Master Configuration Register 0 */
|
||||
#define AT91_MATRIX_MCFG1 (AT91_MATRIX + 0x04) /* Master Configuration Register 1 */
|
||||
#define AT91_MATRIX_MCFG2 (AT91_MATRIX + 0x08) /* Master Configuration Register 2 */
|
||||
#define AT91_MATRIX_MCFG3 (AT91_MATRIX + 0x0C) /* Master Configuration Register 3 */
|
||||
#define AT91_MATRIX_MCFG4 (AT91_MATRIX + 0x10) /* Master Configuration Register 4 */
|
||||
#define AT91_MATRIX_MCFG5 (AT91_MATRIX + 0x14) /* Master Configuration Register 5 */
|
||||
#define AT91_MATRIX_MCFG6 (AT91_MATRIX + 0x18) /* Master Configuration Register 6 */
|
||||
#define AT91_MATRIX_MCFG7 (AT91_MATRIX + 0x1C) /* Master Configuration Register 7 */
|
||||
#define AT91_MATRIX_MCFG8 (AT91_MATRIX + 0x20) /* Master Configuration Register 8 */
|
||||
#define AT91_MATRIX_MCFG9 (AT91_MATRIX + 0x24) /* Master Configuration Register 9 */
|
||||
#define AT91_MATRIX_MCFG10 (AT91_MATRIX + 0x28) /* Master Configuration Register 10 */
|
||||
#define AT91_MATRIX_MCFG11 (AT91_MATRIX + 0x2C) /* Master Configuration Register 11 */
|
||||
#define AT91_MATRIX_ULBT (7 << 0) /* Undefined Length Burst Type */
|
||||
#define AT91_MATRIX_ULBT_INFINITE (0 << 0)
|
||||
#define AT91_MATRIX_ULBT_SINGLE (1 << 0)
|
||||
#define AT91_MATRIX_ULBT_FOUR (2 << 0)
|
||||
#define AT91_MATRIX_ULBT_EIGHT (3 << 0)
|
||||
#define AT91_MATRIX_ULBT_SIXTEEN (4 << 0)
|
||||
#define AT91_MATRIX_ULBT_THIRTYTWO (5 << 0)
|
||||
#define AT91_MATRIX_ULBT_SIXTYFOUR (6 << 0)
|
||||
#define AT91_MATRIX_ULBT_128 (7 << 0)
|
||||
|
||||
#define AT91_MATRIX_SCFG0 (AT91_MATRIX + 0x40) /* Slave Configuration Register 0 */
|
||||
#define AT91_MATRIX_SCFG1 (AT91_MATRIX + 0x44) /* Slave Configuration Register 1 */
|
||||
#define AT91_MATRIX_SCFG2 (AT91_MATRIX + 0x48) /* Slave Configuration Register 2 */
|
||||
#define AT91_MATRIX_SCFG3 (AT91_MATRIX + 0x4C) /* Slave Configuration Register 3 */
|
||||
#define AT91_MATRIX_SCFG4 (AT91_MATRIX + 0x50) /* Slave Configuration Register 4 */
|
||||
#define AT91_MATRIX_SCFG5 (AT91_MATRIX + 0x54) /* Slave Configuration Register 5 */
|
||||
#define AT91_MATRIX_SCFG6 (AT91_MATRIX + 0x58) /* Slave Configuration Register 6 */
|
||||
#define AT91_MATRIX_SCFG7 (AT91_MATRIX + 0x5C) /* Slave Configuration Register 7 */
|
||||
#define AT91_MATRIX_SLOT_CYCLE (0x1ff << 0) /* Maximum Number of Allowed Cycles for a Burst */
|
||||
#define AT91_MATRIX_DEFMSTR_TYPE (3 << 16) /* Default Master Type */
|
||||
#define AT91_MATRIX_DEFMSTR_TYPE_NONE (0 << 16)
|
||||
#define AT91_MATRIX_DEFMSTR_TYPE_LAST (1 << 16)
|
||||
#define AT91_MATRIX_DEFMSTR_TYPE_FIXED (2 << 16)
|
||||
#define AT91_MATRIX_FIXED_DEFMSTR (0xf << 18) /* Fixed Index of Default Master */
|
||||
|
||||
#define AT91_MATRIX_PRAS0 (AT91_MATRIX + 0x80) /* Priority Register A for Slave 0 */
|
||||
#define AT91_MATRIX_PRBS0 (AT91_MATRIX + 0x84) /* Priority Register B for Slave 0 */
|
||||
#define AT91_MATRIX_PRAS1 (AT91_MATRIX + 0x88) /* Priority Register A for Slave 1 */
|
||||
#define AT91_MATRIX_PRBS1 (AT91_MATRIX + 0x8C) /* Priority Register B for Slave 1 */
|
||||
#define AT91_MATRIX_PRAS2 (AT91_MATRIX + 0x90) /* Priority Register A for Slave 2 */
|
||||
#define AT91_MATRIX_PRBS2 (AT91_MATRIX + 0x94) /* Priority Register B for Slave 2 */
|
||||
#define AT91_MATRIX_PRAS3 (AT91_MATRIX + 0x98) /* Priority Register A for Slave 3 */
|
||||
#define AT91_MATRIX_PRBS3 (AT91_MATRIX + 0x9C) /* Priority Register B for Slave 3 */
|
||||
#define AT91_MATRIX_PRAS4 (AT91_MATRIX + 0xA0) /* Priority Register A for Slave 4 */
|
||||
#define AT91_MATRIX_PRBS4 (AT91_MATRIX + 0xA4) /* Priority Register B for Slave 4 */
|
||||
#define AT91_MATRIX_PRAS5 (AT91_MATRIX + 0xA8) /* Priority Register A for Slave 5 */
|
||||
#define AT91_MATRIX_PRBS5 (AT91_MATRIX + 0xAC) /* Priority Register B for Slave 5 */
|
||||
#define AT91_MATRIX_PRAS6 (AT91_MATRIX + 0xB0) /* Priority Register A for Slave 6 */
|
||||
#define AT91_MATRIX_PRBS6 (AT91_MATRIX + 0xB4) /* Priority Register B for Slave 6 */
|
||||
#define AT91_MATRIX_PRAS7 (AT91_MATRIX + 0xB8) /* Priority Register A for Slave 7 */
|
||||
#define AT91_MATRIX_PRBS7 (AT91_MATRIX + 0xBC) /* Priority Register B for Slave 7 */
|
||||
#define AT91_MATRIX_M0PR (3 << 0) /* Master 0 Priority */
|
||||
#define AT91_MATRIX_M1PR (3 << 4) /* Master 1 Priority */
|
||||
#define AT91_MATRIX_M2PR (3 << 8) /* Master 2 Priority */
|
||||
#define AT91_MATRIX_M3PR (3 << 12) /* Master 3 Priority */
|
||||
#define AT91_MATRIX_M4PR (3 << 16) /* Master 4 Priority */
|
||||
#define AT91_MATRIX_M5PR (3 << 20) /* Master 5 Priority */
|
||||
#define AT91_MATRIX_M6PR (3 << 24) /* Master 6 Priority */
|
||||
#define AT91_MATRIX_M7PR (3 << 28) /* Master 7 Priority */
|
||||
#define AT91_MATRIX_M8PR (3 << 0) /* Master 8 Priority (in Register B) */
|
||||
#define AT91_MATRIX_M9PR (3 << 4) /* Master 9 Priority (in Register B) */
|
||||
#define AT91_MATRIX_M10PR (3 << 8) /* Master 10 Priority (in Register B) */
|
||||
#define AT91_MATRIX_M11PR (3 << 12) /* Master 11 Priority (in Register B) */
|
||||
|
||||
#define AT91_MATRIX_MRCR (AT91_MATRIX + 0x100) /* Master Remap Control Register */
|
||||
#define AT91_MATRIX_RCB0 (1 << 0) /* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */
|
||||
#define AT91_MATRIX_RCB1 (1 << 1) /* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */
|
||||
#define AT91_MATRIX_RCB2 (1 << 2)
|
||||
#define AT91_MATRIX_RCB3 (1 << 3)
|
||||
#define AT91_MATRIX_RCB4 (1 << 4)
|
||||
#define AT91_MATRIX_RCB5 (1 << 5)
|
||||
#define AT91_MATRIX_RCB6 (1 << 6)
|
||||
#define AT91_MATRIX_RCB7 (1 << 7)
|
||||
#define AT91_MATRIX_RCB8 (1 << 8)
|
||||
#define AT91_MATRIX_RCB9 (1 << 9)
|
||||
#define AT91_MATRIX_RCB10 (1 << 10)
|
||||
#define AT91_MATRIX_RCB11 (1 << 11)
|
||||
|
||||
#define AT91_MATRIX_TCMR (AT91_MATRIX + 0x110) /* TCM Configuration Register */
|
||||
#define AT91_MATRIX_ITCM_SIZE (0xf << 0) /* Size of ITCM enabled memory block */
|
||||
#define AT91_MATRIX_ITCM_0 (0 << 0)
|
||||
#define AT91_MATRIX_ITCM_32 (6 << 0)
|
||||
#define AT91_MATRIX_DTCM_SIZE (0xf << 4) /* Size of DTCM enabled memory block */
|
||||
#define AT91_MATRIX_DTCM_0 (0 << 4)
|
||||
#define AT91_MATRIX_DTCM_32 (6 << 4)
|
||||
#define AT91_MATRIX_DTCM_64 (7 << 4)
|
||||
#define AT91_MATRIX_TCM_NWS (0x1 << 11) /* Wait state TCM register */
|
||||
#define AT91_MATRIX_TCM_NO_WS (0x0 << 11)
|
||||
#define AT91_MATRIX_TCM_ONE_WS (0x1 << 11)
|
||||
|
||||
#define AT91_MATRIX_VIDEO (AT91_MATRIX + 0x118) /* Video Mode Configuration Register */
|
||||
#define AT91C_VDEC_SEL (0x1 << 0) /* Video Mode Selection */
|
||||
#define AT91C_VDEC_SEL_OFF (0 << 0)
|
||||
#define AT91C_VDEC_SEL_ON (1 << 0)
|
||||
|
||||
#define AT91_MATRIX_EBICSA (AT91_MATRIX + 0x128) /* EBI Chip Select Assignment Register */
|
||||
#define AT91_MATRIX_EBI_CS1A (1 << 1) /* Chip Select 1 Assignment */
|
||||
#define AT91_MATRIX_EBI_CS1A_SMC (0 << 1)
|
||||
#define AT91_MATRIX_EBI_CS1A_SDRAMC (1 << 1)
|
||||
#define AT91_MATRIX_EBI_CS3A (1 << 3) /* Chip Select 3 Assignment */
|
||||
#define AT91_MATRIX_EBI_CS3A_SMC (0 << 3)
|
||||
#define AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA (1 << 3)
|
||||
#define AT91_MATRIX_EBI_CS4A (1 << 4) /* Chip Select 4 Assignment */
|
||||
#define AT91_MATRIX_EBI_CS4A_SMC (0 << 4)
|
||||
#define AT91_MATRIX_EBI_CS4A_SMC_CF0 (1 << 4)
|
||||
#define AT91_MATRIX_EBI_CS5A (1 << 5) /* Chip Select 5 Assignment */
|
||||
#define AT91_MATRIX_EBI_CS5A_SMC (0 << 5)
|
||||
#define AT91_MATRIX_EBI_CS5A_SMC_CF1 (1 << 5)
|
||||
#define AT91_MATRIX_EBI_DBPUC (1 << 8) /* Data Bus Pull-up Configuration */
|
||||
#define AT91_MATRIX_EBI_DBPU_ON (0 << 8)
|
||||
#define AT91_MATRIX_EBI_DBPU_OFF (1 << 8)
|
||||
#define AT91_MATRIX_EBI_VDDIOMSEL (1 << 16) /* Memory voltage selection */
|
||||
#define AT91_MATRIX_EBI_VDDIOMSEL_1_8V (0 << 16)
|
||||
#define AT91_MATRIX_EBI_VDDIOMSEL_3_3V (1 << 16)
|
||||
#define AT91_MATRIX_EBI_EBI_IOSR (1 << 17) /* EBI I/O slew rate selection */
|
||||
#define AT91_MATRIX_EBI_EBI_IOSR_REDUCED (0 << 17)
|
||||
#define AT91_MATRIX_EBI_EBI_IOSR_NORMAL (1 << 17)
|
||||
#define AT91_MATRIX_EBI_DDR_IOSR (1 << 18) /* DDR2 dedicated port I/O slew rate selection */
|
||||
#define AT91_MATRIX_EBI_DDR_IOSR_REDUCED (0 << 18)
|
||||
#define AT91_MATRIX_EBI_DDR_IOSR_NORMAL (1 << 18)
|
||||
|
||||
#define AT91_MATRIX_WPMR (AT91_MATRIX + 0x1E4) /* Write Protect Mode Register */
|
||||
#define AT91_MATRIX_WPMR_WPEN (1 << 0) /* Write Protect ENable */
|
||||
#define AT91_MATRIX_WPMR_WP_WPDIS (0 << 0)
|
||||
#define AT91_MATRIX_WPMR_WP_WPEN (1 << 0)
|
||||
#define AT91_MATRIX_WPMR_WPKEY (0xFFFFFF << 8) /* Write Protect KEY */
|
||||
|
||||
#define AT91_MATRIX_WPSR (AT91_MATRIX + 0x1E8) /* Write Protect Status Register */
|
||||
#define AT91_MATRIX_WPSR_WPVS (1 << 0) /* Write Protect Violation Status */
|
||||
#define AT91_MATRIX_WPSR_NO_WPV (0 << 0)
|
||||
#define AT91_MATRIX_WPSR_WPV (1 << 0)
|
||||
#define AT91_MATRIX_WPSR_WPVSRC (0xFFFF << 8) /* Write Protect Violation Source */
|
||||
|
||||
#endif
|
||||
@@ -49,6 +49,11 @@ static inline unsigned long get_lcdc_clk_rate(unsigned int dev_id)
|
||||
return get_mck_clk_rate();
|
||||
}
|
||||
|
||||
static inline unsigned long get_spi_clk_rate(unsigned int dev_id)
|
||||
{
|
||||
return get_mck_clk_rate();
|
||||
}
|
||||
|
||||
static inline unsigned long get_twi_clk_rate(unsigned int dev_id)
|
||||
{
|
||||
return get_mck_clk_rate();
|
||||
|
||||
@@ -23,7 +23,7 @@
|
||||
#define AT91_BASE_SPI AT91SAM9260_BASE_SPI0
|
||||
#define AT91_ID_UHP AT91SAM9260_ID_UHP
|
||||
#define AT91_PMC_UHP AT91SAM926x_PMC_UHP
|
||||
#elif defined(CONFIG_AT91SAM9261)
|
||||
#elif defined(CONFIG_AT91SAM9261) || defined(CONFIG_AT91SAM9G10)
|
||||
#include <asm/arch/at91sam9261.h>
|
||||
#define AT91_BASE_SPI AT91SAM9261_BASE_SPI0
|
||||
#define AT91_ID_UHP AT91SAM9261_ID_UHP
|
||||
@@ -37,6 +37,12 @@
|
||||
#include <asm/arch/at91sam9rl.h>
|
||||
#define AT91_BASE_SPI AT91SAM9RL_BASE_SPI
|
||||
#define AT91_ID_UHP AT91SAM9RL_ID_UHP
|
||||
#elif defined(CONFIG_AT91SAM9G45) || defined(CONFIG_AT91SAM9M10G45)
|
||||
#include <asm/arch/at91sam9g45.h>
|
||||
#define AT91_BASE_EMAC AT91SAM9G45_BASE_EMAC
|
||||
#define AT91_BASE_SPI AT91SAM9G45_BASE_SPI0
|
||||
#define AT91_ID_UHP AT91SAM9G45_ID_UHPHS
|
||||
#define AT91_PMC_UHP AT91SAM926x_PMC_UHP
|
||||
#elif defined(CONFIG_AT91CAP9)
|
||||
#include <asm/arch/at91cap9.h>
|
||||
#define AT91_BASE_SPI AT91CAP9_BASE_SPI0
|
||||
|
||||
@@ -30,5 +30,6 @@
|
||||
#define USART1_BASE AT91_USART1
|
||||
#define USART2_BASE AT91_USART2
|
||||
#define USART3_BASE (AT91_BASE_SYS + AT91_DBGU)
|
||||
#define SPI0_BASE AT91_BASE_SPI
|
||||
|
||||
#endif /* __ASM_ARM_ARCH_MEMORYMAP_H__ */
|
||||
|
||||
@@ -45,7 +45,7 @@
|
||||
#define KW_REG_UNDOC_0x1478 (KW_REGISTER(0x1478))
|
||||
|
||||
#define KW_UART0_BASE (KW_REGISTER(0x12000))
|
||||
#define KW_UART1_BASE (KW_REGISTER(0x13000))
|
||||
#define KW_UART1_BASE (KW_REGISTER(0x12100))
|
||||
#define KW_MPP_BASE (KW_REGISTER(0x10000))
|
||||
#define KW_GPIO0_BASE (KW_REGISTER(0x10100))
|
||||
#define KW_GPIO1_BASE (KW_REGISTER(0x10140))
|
||||
|
||||
@@ -1952,12 +1952,13 @@ typedef void (*ExcpHndlr) (void) ;
|
||||
#define CKENA_2_USBHOST (1 << 2) /* USB Host Unit Clock Enable */
|
||||
#define CKENA_1_LCD (1 << 1) /* LCD Unit Clock Enable */
|
||||
|
||||
#define CKENB_8_1WIRE ((1 << 8) + 32) /* One Wire Interface Unit Clock Enable */
|
||||
#define CKENB_7_GPIO ((1 << 7) + 32) /* GPIO Clock Enable */
|
||||
#define CKENB_6_IRQ ((1 << 6) + 32) /* Interrupt Controller Clock Enable */
|
||||
#define CKENB_4_I2C ((1 << 4) + 32) /* I2C Unit Clock Enable */
|
||||
#define CKENB_1_PWM1 ((1 << 1) + 32) /* PWM2 & PWM3 Clock Enable */
|
||||
#define CKENB_0_PWM0 ((1 << 0) + 32) /* PWM0 & PWM1 Clock Enable */
|
||||
#define CKENB_9_SYSBUS2 (1 << 9) /* System bus 2 */
|
||||
#define CKENB_8_1WIRE (1 << 8) /* One Wire Interface Unit Clock Enable */
|
||||
#define CKENB_7_GPIO (1 << 7) /* GPIO Clock Enable */
|
||||
#define CKENB_6_IRQ (1 << 6) /* Interrupt Controller Clock Enable */
|
||||
#define CKENB_4_I2C (1 << 4) /* I2C Unit Clock Enable */
|
||||
#define CKENB_1_PWM1 (1 << 1) /* PWM2 & PWM3 Clock Enable */
|
||||
#define CKENB_0_PWM0 (1 << 0) /* PWM0 & PWM1 Clock Enable */
|
||||
|
||||
#else /* if defined CONFIG_CPU_MONAHANS */
|
||||
|
||||
|
||||
@@ -32,8 +32,11 @@
|
||||
#define CONFIG_SYS_HZ 1000
|
||||
|
||||
#define CONFIG_ARM926EJS 1 /* This is an ARM926EJS Core */
|
||||
#ifdef CONFIG_AT91SAM9G10EK
|
||||
#define CONFIG_AT91SAM9G10 1 /* It's an Atmel AT91SAM9G10 SoC*/
|
||||
#else
|
||||
#define CONFIG_AT91SAM9261 1 /* It's an Atmel AT91SAM9261 SoC*/
|
||||
#define CONFIG_AT91SAM9261EK 1 /* on an AT91SAM9261EK Board */
|
||||
#endif
|
||||
#define CONFIG_ARCH_CPU_INIT
|
||||
#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
|
||||
|
||||
@@ -62,7 +65,11 @@
|
||||
#define CONFIG_LCD_INFO_BELOW_LOGO 1
|
||||
#define CONFIG_SYS_WHITE_ON_BLACK 1
|
||||
#define CONFIG_ATMEL_LCD 1
|
||||
#ifdef CONFIG_AT91SAM9261EK
|
||||
#define CONFIG_ATMEL_LCD_BGR555 1
|
||||
#else
|
||||
#define CONFIG_AT91SAM9G10_LCD_BASE 0x23E00000 /* LCD is no more in SRAM */
|
||||
#endif
|
||||
#define CONFIG_SYS_CONSOLE_IS_IN_ENV 1
|
||||
|
||||
/* LED */
|
||||
@@ -147,7 +154,11 @@
|
||||
#define CONFIG_DOS_PARTITION 1
|
||||
#define CONFIG_SYS_USB_OHCI_CPU_INIT 1
|
||||
#define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00500000 /* AT91SAM9261_UHP_BASE */
|
||||
#ifdef CONFIG_AT91SAM9G10EK
|
||||
#define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9g10"
|
||||
#else
|
||||
#define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9261"
|
||||
#endif
|
||||
#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2
|
||||
#define CONFIG_USB_STORAGE 1
|
||||
#define CONFIG_CMD_FAT 1
|
||||
|
||||
225
include/configs/at91sam9m10g45ek.h
Normal file
225
include/configs/at91sam9m10g45ek.h
Normal file
@@ -0,0 +1,225 @@
|
||||
/*
|
||||
* (C) Copyright 2007-2008
|
||||
* Stelian Pop <stelian.pop@leadtechdesign.com>
|
||||
* Lead Tech Design <www.leadtechdesign.com>
|
||||
*
|
||||
* Configuation settings for the AT91SAM9M10G45EK board(and AT91SAM9G45EKES).
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#ifndef __CONFIG_H
|
||||
#define __CONFIG_H
|
||||
|
||||
/* ARM asynchronous clock */
|
||||
#define AT91_MAIN_CLOCK 12000000 /* from 12 MHz crystal */
|
||||
#define CONFIG_SYS_HZ 1000
|
||||
|
||||
#define CONFIG_ARM926EJS 1 /* This is an ARM926EJS Core */
|
||||
#ifdef CONFIG_AT91SAM9M10G45EK
|
||||
#define CONFIG_AT91SAM9M10G45 1 /* It's an Atmel AT91SAM9M10G45 SoC*/
|
||||
#else
|
||||
#define CONFIG_AT91SAM9G45 1 /* It's an Atmel AT91SAM9G45 SoC*/
|
||||
#endif
|
||||
#define CONFIG_ARCH_CPU_INIT
|
||||
#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
|
||||
|
||||
#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
|
||||
#define CONFIG_SETUP_MEMORY_TAGS 1
|
||||
#define CONFIG_INITRD_TAG 1
|
||||
|
||||
#define CONFIG_SKIP_LOWLEVEL_INIT
|
||||
#define CONFIG_SKIP_RELOCATE_UBOOT
|
||||
|
||||
/*
|
||||
* Hardware drivers
|
||||
*/
|
||||
#define CONFIG_ATMEL_USART 1
|
||||
#undef CONFIG_USART0
|
||||
#undef CONFIG_USART1
|
||||
#undef CONFIG_USART2
|
||||
#define CONFIG_USART3 1 /* USART 3 is DBGU */
|
||||
|
||||
/* LCD */
|
||||
#define CONFIG_LCD 1
|
||||
#define LCD_BPP LCD_COLOR8
|
||||
#define CONFIG_LCD_LOGO 1
|
||||
#undef LCD_TEST_PATTERN
|
||||
#define CONFIG_LCD_INFO 1
|
||||
#define CONFIG_LCD_INFO_BELOW_LOGO 1
|
||||
#define CONFIG_SYS_WHITE_ON_BLACK 1
|
||||
#define CONFIG_ATMEL_LCD 1
|
||||
#define CONFIG_ATMEL_LCD_RGB565 1
|
||||
#define CONFIG_SYS_CONSOLE_IS_IN_ENV 1
|
||||
/* board specific(not enough SRAM) */
|
||||
#define CONFIG_AT91SAM9G45_LCD_BASE 0x73E00000
|
||||
|
||||
/* LED */
|
||||
#define CONFIG_AT91_LED
|
||||
#define CONFIG_RED_LED AT91_PIN_PD31 /* this is the user1 led */
|
||||
#define CONFIG_GREEN_LED AT91_PIN_PD0 /* this is the user2 led */
|
||||
|
||||
#define CONFIG_BOOTDELAY 3
|
||||
|
||||
/*
|
||||
* BOOTP options
|
||||
*/
|
||||
#define CONFIG_BOOTP_BOOTFILESIZE 1
|
||||
#define CONFIG_BOOTP_BOOTPATH 1
|
||||
#define CONFIG_BOOTP_GATEWAY 1
|
||||
#define CONFIG_BOOTP_HOSTNAME 1
|
||||
|
||||
/*
|
||||
* Command line configuration.
|
||||
*/
|
||||
#include <config_cmd_default.h>
|
||||
#undef CONFIG_CMD_BDI
|
||||
#undef CONFIG_CMD_FPGA
|
||||
#undef CONFIG_CMD_IMI
|
||||
#undef CONFIG_CMD_IMLS
|
||||
#undef CONFIG_CMD_AUTOSCRIPT
|
||||
#undef CONFIG_CMD_LOADS
|
||||
|
||||
#define CONFIG_CMD_PING 1
|
||||
#define CONFIG_CMD_DHCP 1
|
||||
#define CONFIG_CMD_NAND 1
|
||||
#define CONFIG_CMD_USB 1
|
||||
|
||||
/* SDRAM */
|
||||
#define CONFIG_NR_DRAM_BANKS 1
|
||||
#define PHYS_SDRAM 0x70000000
|
||||
#define PHYS_SDRAM_SIZE 0x08000000 /* 128 megs */
|
||||
|
||||
/* DataFlash */
|
||||
#ifdef CONFIG_ATMEL_SPI
|
||||
#define CONFIG_CMD_SF
|
||||
#define CONFIG_CMD_SPI
|
||||
#define CONFIG_SPI_FLASH 1
|
||||
#define CONFIG_SPI_FLASH_ATMEL 1
|
||||
#define CONFIG_SYS_MAX_DATAFLASH_BANKS 1
|
||||
#endif
|
||||
|
||||
/* NOR flash, if populated */
|
||||
#ifndef CONFIG_CMD_NAND
|
||||
#define CONFIG_SYS_NO_FLASH 1
|
||||
#else
|
||||
#define CONFIG_SYS_FLASH_CFI 1
|
||||
#define CONFIG_FLASH_CFI_DRIVER 1
|
||||
#define PHYS_FLASH_1 0x10000000
|
||||
#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
|
||||
#define CONFIG_SYS_MAX_FLASH_SECT 256
|
||||
#define CONFIG_SYS_MAX_FLASH_BANKS 1
|
||||
#endif
|
||||
|
||||
/* NAND flash */
|
||||
#ifdef CONFIG_CMD_NAND
|
||||
#define CONFIG_NAND_MAX_CHIPS 1
|
||||
#define CONFIG_NAND_ATMEL
|
||||
#define CONFIG_SYS_MAX_NAND_DEVICE 1
|
||||
#define CONFIG_SYS_NAND_BASE 0x40000000
|
||||
#define CONFIG_SYS_NAND_DBW_8 1
|
||||
/* our ALE is AD21 */
|
||||
#define CONFIG_SYS_NAND_MASK_ALE (1 << 21)
|
||||
/* our CLE is AD22 */
|
||||
#define CONFIG_SYS_NAND_MASK_CLE (1 << 22)
|
||||
#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PC14
|
||||
#define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PC8
|
||||
#endif
|
||||
|
||||
/* Ethernet */
|
||||
#define CONFIG_MACB 1
|
||||
#define CONFIG_RMII 1
|
||||
#define CONFIG_NET_MULTI 1
|
||||
#define CONFIG_NET_RETRY_COUNT 20
|
||||
#define CONFIG_RESET_PHY_R 1
|
||||
|
||||
/* USB */
|
||||
#define CONFIG_USB_ATMEL
|
||||
#define CONFIG_USB_OHCI_NEW 1
|
||||
#define CONFIG_DOS_PARTITION 1
|
||||
#define CONFIG_SYS_USB_OHCI_CPU_INIT 1
|
||||
#define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00700000 /* AT91SAM9G45_UHP_OHCI_BASE */
|
||||
#define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9g45"
|
||||
#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2
|
||||
#define CONFIG_USB_STORAGE 1
|
||||
|
||||
#define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */
|
||||
|
||||
#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM
|
||||
#define CONFIG_SYS_MEMTEST_END 0x23e00000
|
||||
|
||||
#ifdef CONFIG_SYS_USE_DATAFLASH
|
||||
|
||||
/* bootstrap + u-boot + env + linux in dataflash on CS0 */
|
||||
#define CONFIG_ENV_IS_IN_SPI_FLASH 1
|
||||
#define CONFIG_SYS_MONITOR_BASE (0xC0000000 + 0x8400)
|
||||
#define CONFIG_ENV_OFFSET 0x4200
|
||||
#define CONFIG_ENV_ADDR (0xC0000000 + CONFIG_ENV_OFFSET)
|
||||
#define CONFIG_ENV_SIZE 0x4200
|
||||
#define CONFIG_ENV_SECT_SIZE 0x10000
|
||||
#define CONFIG_BOOTCOMMAND "cp.b 0xC0042000 0x22000000 0x210000; bootm"
|
||||
#define CONFIG_BOOTARGS "console=ttyS0,115200 " \
|
||||
"root=/dev/mtdblock0 " \
|
||||
"mtdparts=at91_nand:-(root) "\
|
||||
"rw rootfstype=jffs2"
|
||||
|
||||
#else /* CONFIG_SYS_USE_NANDFLASH */
|
||||
|
||||
/* bootstrap + u-boot + env + linux in nandflash */
|
||||
#define CONFIG_ENV_IS_IN_NAND 1
|
||||
#define CONFIG_ENV_OFFSET 0x60000
|
||||
#define CONFIG_ENV_OFFSET_REDUND 0x80000
|
||||
#define CONFIG_ENV_SIZE 0x20000 /* 1 sector = 128 kB */
|
||||
#define CONFIG_BOOTCOMMAND "nand read 0x72000000 0x200000 0x200000; bootm"
|
||||
#define CONFIG_BOOTARGS "console=ttyS0,115200 " \
|
||||
"root=/dev/mtdblock5 " \
|
||||
"mtdparts=at91_nand:128k(bootstrap)ro, \
|
||||
256k(uboot)ro,128k(env1)ro,128k(env2)ro, \
|
||||
2M(linux),-(root) " \
|
||||
"rw rootfstype=jffs2"
|
||||
|
||||
#endif
|
||||
|
||||
#define CONFIG_BAUDRATE 115200
|
||||
#define CONFIG_SYS_BAUDRATE_TABLE {115200 , 19200, 38400, 57600, 9600 }
|
||||
|
||||
#define CONFIG_SYS_PROMPT "U-Boot> "
|
||||
#define CONFIG_SYS_CBSIZE 256
|
||||
#define CONFIG_SYS_MAXARGS 16
|
||||
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
|
||||
#define CONFIG_SYS_LONGHELP 1
|
||||
#define CONFIG_CMDLINE_EDITING 1
|
||||
#define CONFIG_AUTO_COMPLETE
|
||||
#define CONFIG_SYS_HUSH_PARSER
|
||||
#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
|
||||
|
||||
#define ROUND(A, B) (((A) + (B)) & ~((B) - 1))
|
||||
/*
|
||||
* Size of malloc() pool
|
||||
*/
|
||||
#define CONFIG_SYS_MALLOC_LEN ROUND(3 * CONFIG_ENV_SIZE + 128*1024, 0x1000)
|
||||
#define CONFIG_SYS_GBL_DATA_SIZE 128 /* 128 bytes for initial data */
|
||||
|
||||
#define CONFIG_STACKSIZE (32*1024) /* regular stack */
|
||||
|
||||
#ifdef CONFIG_USE_IRQ
|
||||
#error CONFIG_USE_IRQ not supported
|
||||
#endif
|
||||
|
||||
#endif
|
||||
@@ -39,6 +39,10 @@
|
||||
#define CONFIG_VERSATILE 1 /* in Versatile Platform Board */
|
||||
#define CONFIG_ARCH_VERSATILE 1 /* Specifically, a Versatile */
|
||||
|
||||
#ifndef CONFIG_ARCH_VERSATILE_AB /* AB */
|
||||
#define CONFIG_ARCH_VERSATILE_PB /* Versatile PB is default */
|
||||
#endif
|
||||
|
||||
#define CONFIG_SYS_MEMTEST_START 0x100000
|
||||
#define CONFIG_SYS_MEMTEST_END 0x10000000
|
||||
#define CONFIG_SYS_HZ (1000000 / 256)
|
||||
@@ -101,7 +105,6 @@
|
||||
/*
|
||||
* Command line configuration.
|
||||
*/
|
||||
|
||||
#define CONFIG_CMD_BDI
|
||||
#define CONFIG_CMD_DHCP
|
||||
#define CONFIG_CMD_FLASH
|
||||
@@ -132,8 +135,13 @@
|
||||
* Miscellaneous configurable options
|
||||
*/
|
||||
#define CONFIG_SYS_LONGHELP /* undef to save memory */
|
||||
#define CONFIG_SYS_PROMPT "Versatile # " /* Monitor Command Prompt */
|
||||
#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
|
||||
/* Monitor Command Prompt */
|
||||
#ifdef CONFIG_ARCH_VERSATILE_AB
|
||||
# define CONFIG_SYS_PROMPT "VersatileAB # "
|
||||
#else
|
||||
# define CONFIG_SYS_PROMPT "VersatilePB # "
|
||||
#endif
|
||||
/* Print Buffer Size */
|
||||
#define CONFIG_SYS_PBSIZE \
|
||||
(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
|
||||
@@ -159,13 +167,20 @@
|
||||
#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
|
||||
#define PHYS_SDRAM_1 0x00000000 /* SDRAM Bank #1 */
|
||||
#define PHYS_SDRAM_1_SIZE 0x08000000 /* 128 MB */
|
||||
|
||||
#define CONFIG_SYS_FLASH_BASE 0x34000000
|
||||
#define PHYS_FLASH_SIZE 0x04000000 /* 64MB */
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* FLASH and environment organization
|
||||
*/
|
||||
|
||||
/*
|
||||
* Use the CFI flash driver for ease of use
|
||||
*/
|
||||
#define CONFIG_SYS_FLASH_CFI
|
||||
#define CONFIG_FLASH_CFI_DRIVER
|
||||
#define CONFIG_ENV_IS_IN_FLASH 1
|
||||
/*
|
||||
* System control register
|
||||
*/
|
||||
#define VERSATILE_SYS_BASE 0x10000000
|
||||
#define VERSATILE_SYS_FLASH_OFFSET 0x4C
|
||||
#define VERSATILE_FLASHCTRL \
|
||||
@@ -173,19 +188,47 @@
|
||||
/* Enable writing to flash */
|
||||
#define VERSATILE_FLASHPROG_FLVPPEN (1 << 0)
|
||||
|
||||
#define CONFIG_SYS_MAX_FLASH_BANKS 1
|
||||
#define PHYS_FLASH_SIZE 0x34000000 /* 64MB */
|
||||
/* timeout values are in ticks */
|
||||
#define CONFIG_SYS_FLASH_ERASE_TOUT (20 * CONFIG_SYS_HZ) /* Erase Timeout */
|
||||
#define CONFIG_SYS_FLASH_WRITE_TOUT (20 * CONFIG_SYS_HZ) /* Write Timeout */
|
||||
#define CONFIG_SYS_MAX_FLASH_SECT (256)
|
||||
#define CONFIG_SYS_FLASH_ERASE_TOUT (2 * CONFIG_SYS_HZ) /* Erase Timeout */
|
||||
#define CONFIG_SYS_FLASH_WRITE_TOUT (2 * CONFIG_SYS_HZ) /* Write Timeout */
|
||||
|
||||
#define PHYS_FLASH_1 (CONFIG_SYS_FLASH_BASE)
|
||||
/*
|
||||
* Note that CONFIG_SYS_MAX_FLASH_SECT allows for a parameter block
|
||||
* i.e.
|
||||
* the bottom "sector" (bottom boot), or top "sector"
|
||||
* (top boot), is a seperate erase region divided into
|
||||
* 4 (equal) smaller sectors. This, notionally, allows
|
||||
* quicker erase/rewrire of the most frequently changed
|
||||
* area......
|
||||
* CONFIG_SYS_MAX_FLASH_SECT is padded up to a multiple of 4
|
||||
*/
|
||||
|
||||
#define CONFIG_ENV_IS_IN_FLASH 1 /* env in flash */
|
||||
#define CONFIG_ENV_SECT_SIZE 0x00020000 /* 256 KB sectors (x2) */
|
||||
#define CONFIG_ENV_SIZE 0x10000 /* Size of Environment */
|
||||
#define CONFIG_ENV_OFFSET 0x01f00000 /* environment starts */
|
||||
#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET)
|
||||
#ifdef CONFIG_ARCH_VERSATILE_AB
|
||||
#define FLASH_SECTOR_SIZE 0x00020000 /* 128 KB sectors */
|
||||
#define CONFIG_ENV_SECT_SIZE (2 * FLASH_SECTOR_SIZE)
|
||||
#define CONFIG_SYS_MAX_FLASH_SECT (520)
|
||||
#endif
|
||||
|
||||
#endif /* __CONFIG_H */
|
||||
#ifdef CONFIG_ARCH_VERSATILE_PB /* Versatile PB is default */
|
||||
#define FLASH_SECTOR_SIZE 0x00040000 /* 256 KB sectors */
|
||||
#define CONFIG_ENV_SECT_SIZE FLASH_SECTOR_SIZE
|
||||
#define CONFIG_SYS_MAX_FLASH_SECT (260)
|
||||
#endif
|
||||
|
||||
#define CONFIG_SYS_FLASH_BASE 0x34000000
|
||||
#define CONFIG_SYS_MAX_FLASH_BANKS 1
|
||||
|
||||
#define CONFIG_SYS_MONITOR_LEN (4 * CONFIG_ENV_SECT_SIZE)
|
||||
|
||||
/* The ARM Boot Monitor is shipped in the lowest sector of flash */
|
||||
|
||||
#define FLASH_TOP (CONFIG_SYS_FLASH_BASE + PHYS_FLASH_SIZE)
|
||||
#define CONFIG_ENV_SIZE 8192
|
||||
#define CONFIG_ENV_ADDR (FLASH_TOP - CONFIG_ENV_SECT_SIZE)
|
||||
#define CONFIG_ENV_OFFSET (CONFIG_ENV_ADDR - CONFIG_SYS_FLASH_BASE)
|
||||
#define CONFIG_SYS_MONITOR_BASE (CONFIG_ENV_ADDR - CONFIG_SYS_MONITOR_LEN)
|
||||
|
||||
#define CONFIG_SYS_FLASH_PROTECTION /* The devices have real protection */
|
||||
#define CONFIG_SYS_FLASH_EMPTY_INFO /* flinfo indicates empty blocks */
|
||||
|
||||
#endif /* __CONFIG_H */
|
||||
|
||||
Reference in New Issue
Block a user