Merge branch 'master' of git://git.denx.de/u-boot-arm
* 'master' of git://git.denx.de/u-boot-arm: (146 commits)
arm: Use common .lds file where possible
arm: add a common .lds link script
arm: Remove unneeded setting of LDCSRIPT
Define CPUDIR for the .lds link script
arm: Remove zipitz2 link script
Allow arch directory to contain .lds without requiring Makefile
OMAP: Remove omap1610inn-based boards
arch/arm/cpu/armv7/omap-common/clocks-common.c: Fix build warnings
board/ti/beagle/beagle.c: Fix build warnings
sdrc.c: Fix typo in do_sdrc_init() for SPL
tegra: i2c: Add I2C driver
tegra: fdt: i2c: Add extra I2C bindings for U-Boot
tegra: i2c: Select I2C ordering for Seaboard
tegra: i2c: Enable I2C on Seaboard
tegra: i2c: Select number of controllers for Tegra2 boards
tegra: i2c: Initialise I2C on Nvidia boards
tegra: Enhance clock support to handle 16-bit clock divisors
fdt: Add function to allow aliases to refer to multiple nodes
tegra: Rename NV_PA_PMC_BASE to TEGRA2_PMC_BASE
tegra: fdt: Enable FDT support for Ventana
tegra: fdt: Enable FDT support for Seaboard
tegra: usb: Enable USB on Seaboard
tegra: usb: Add common USB defines for tegra2 boards
tegra: usb: Add USB support to nvidia boards
arm: Check for valid FDT after console is up
fdt: Avoid early panic() when there is no FDT present
tegra: usb: Add support for Tegra USB peripheral
tegra: fdt: Add function to return peripheral/clock ID
usb: Add support for txfifo threshold
tegra: usb: fdt: Add USB definitions for Tegra2 Seaboard
tegra: usb: fdt: Add additional device tree definitions for USB ports
tegra: fdt: Add clock bindings for Tegra2 Seaboard
tegra: fdt: Add clock bindings
tegra: fdt: Add additional USB binding
fdt: Add tegra-usb bindings file from linux
fdt: Add staging area for device tree binding documentation
tegra: fdt: Add device tree file for Tegra2 Seaboard from kernel
tegra: fdt: Add Tegra2x device tree file from kernel
arm: fdt: Add skeleton device tree file from kernel
fdt: Add basic support for decoding GPIO definitions
fdt: Add functions to access phandles, arrays and bools
fdt: Tidy up a few fdtdec problems
fdt: Add tests for fdtdec
fdt: Add fdtdec_find_aliases() to deal with alias nodes
arm: Tegra2: Fix ELDK42 gcc failure with inline asm stack pointer load
net: fec_mxc: allow use with cache enabled
net: force PKTALIGN to ARCH_DMA_MINALIGN
i.MX28: Enable caches by default
i.MX28: Make use of the bounce buffer
i.MX28: Do data transfers via DMA in MMC driver
MMC: Implement generic bounce buffer
i.MX28: Add cache support to MXS NAND driver
i.MX28: Add cache support into the APBH DMA driver
ARM926EJS: Implement cache operations
board/vpac270/onenand.c: Fix build errors
nhk8815: fix build errors
atmel-boards: add missing atmel_mci.h
ARM: highbank: setup env from boot source register
ARM: highbank: change env config to use nvram
ARM: highbank: add reset support
ARM: highbank: Add boot counter support
ARM: highbank: change TEXT_BASE to 0x8000
ARM: highbank: fix us_to_tick calculation
ARM: highbank: add missing get_tbclk
ARM: highbank: fix warning for calxedaxgmac_initialize
net: calxedaxgmac: fix build due to missing __aligned definition
EXYNOS: Add structure for Exynos4 DMC
EXYNOS: SMDK5250: Support all 4 UARTs
ARM: fix s3c2410 timer code
ARM: davinci: fixes for cam_enc_4xx board
omap3_spi: receive transmit mode
calimain, enbw_cmc: Fix typo in comments
Davinci: ea20: use gpio framework to access gpios
OMAP3: mt_ventoux: sets its own mtdparts
OMAP3: mt_ventoux: updated timing for FPGA
twl4030: fix potential power supply handling issues
NAND: TI: fix warnings in omap_gpmc.c
cam_enc_4xx: Rename 'images' to 'imgs'
arm: Add Prep subcommand support to bootm
OMAP3: twister: add support to boot Linux from SPL
SPL: call cleanup_before_linux() before booting Linux
OMAP3: SPL: do not call I2C init if no I2C is set.
Add cache functions to SPL for armv7
devkit8000: Implement and activate direct OS boot
omap/spl: change output of spl_parse_image_header
omap-common/spl: Add linux boot to SPL
devkit8000/spl: init GPMC for dm9000 in SPL
omap-common: Add NAND SPL linux booting
devkit8000: add config for spl command
Add cmd_spl command
mx53ard: Initialize return code with error
mx53: Make PLL2 to be the parent of UART clock
configs: imx: Use CONFIG_SF_DEFAULT_CS
mx28evk: Provide default values for SPI bus and chip select
USB: ehci-mx6: Add proper IO accessors
mx6: Read silicon revision from register
i.MX28: Drop __naked function from spl_mem_init
mxs_spi: Return proper timeout error
i.MX28: Make the stabilization delays shorter
pmic_i2c: Return error in case of invalid pmic_i2c_tx_num
mx6: Remove duplicate definition of ANATOP_BASE_ADDR
mx6: Fix reset cause for Power On Reset case
i.MX6: mx6qsabrelite: add MACH_TYPE_MX6Q_SABRELITE
i.MX6: mx6q_sabrelite: add CONFIG_REVISION_TAG
i.MX28: Enable additional DRAM address bits
mx6q: mx6qsabrelite: setup_spi() should be called in board_init to allow use for environment
mx31: add "ARM11P power gating" to get_reset_cause
mx31pdk: Fix CONFIG_SYS_MEMTEST_END
efikamx: Fix CONFIG_SYS_MEMTEST_END
mx53smd: Fix CONFIG_SYS_MEMTEST_END
mx53evk: Fix CONFIG_SYS_MEMTEST_END
mx51evk: Fix CONFIG_SYS_MEMTEST_END
i.MX6: mx6qsabrelite: add ext2 support
imximage: Remove overwriting of flash_offset
IXP: Fix GPIO_INT_ACT_LOW_SET()
IXP: Fix NAND build warning on PDNB3 and SCPU
IXP: Move PDNB3 and SCPU from Makefile to boards.cfg
IXP: Squash warnings in IXP NPE
IXP: Fix missing MACH_TYPE_{ACTUX?,PNB3,DVLHOST}
IXP: Make IXP buildable with arm-linux- toolchains
Examples: Properly append LDFLAGS to LD command
SPL: Enable YMODEM support on BeagleBone and AM335x EVM
SPL: Add YMODEM over UART load support
SPL: Add README.omap3
README: document more SPL config options
spl.c: Use __noreturn decorator
config.mk: Check for -fstack-usage support
config.mk: Make cc-option create a file under include/generated
...
This commit is contained in:
Wolfgang Denk
@@ -1,56 +0,0 @@
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These are brief instructions on how to add support for CF adapters to
|
||||
custom designed PXA boards. You need to set the parameters in the
|
||||
config file. This should work for most implementations especially if you
|
||||
follow the connections of the standard lubbock. Anyway just the block
|
||||
marked memory configuration should be touched since the other parameters
|
||||
are imposed by the PXA architecture.
|
||||
|
||||
EDIT 2010-07-01: in common/cmd_ide.c, having CONFIG_PXA_PCMCIA defined
|
||||
would cause looping on inw()/outw() rather than using insw()/outsw(),
|
||||
thus making sure IDE / ATA bytes are properly swapped. This behaviour
|
||||
is now controlled by CONFIG_IDE_SWAP_IO, therefore PXA boards with
|
||||
PCMCIA should #define CONFIG_IDE_SWAP_IO.
|
||||
|
||||
#define CONFIG_IDE_SWAP_IO
|
||||
|
||||
#define CONFIG_PXA_PCMCIA 1
|
||||
#define CONFIG_PXA_IDE 1
|
||||
|
||||
#define CONFIG_PCMCIA_SLOT_A 1
|
||||
/* just to keep build system happy */
|
||||
|
||||
#define CONFIG_SYS_PCMCIA_MEM_ADDR 0x28000000
|
||||
#define CONFIG_SYS_PCMCIA_MEM_SIZE 0x10000000
|
||||
|
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#define CONFIG_SYS_MECR_VAL 0x00000000
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||||
#define CONFIG_SYS_MCMEM0_VAL 0x00004204
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#define CONFIG_SYS_MCMEM1_VAL 0x00000000
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#define CONFIG_SYS_MCATT0_VAL 0x00010504
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#define CONFIG_SYS_MCATT1_VAL 0x00000000
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#define CONFIG_SYS_MCIO0_VAL 0x00008407
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#define CONFIG_SYS_MCIO1_VAL 0x00000000
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/* memory configuration */
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#define CONFIG_SYS_IDE_MAXBUS 1
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/* max. 1 IDE bus */
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#define CONFIG_SYS_IDE_MAXDEVICE 1
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/* max. 1 drive per IDE bus */
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#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
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#define CONFIG_SYS_ATA_BASE_ADDR 0x20000000
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/* Offset for data I/O */
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#define CONFIG_SYS_ATA_DATA_OFFSET 0x1f0
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/* Offset for normal register accesses */
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#define CONFIG_SYS_ATA_REG_OFFSET 0x1f0
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/* Offset for alternate registers */
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#define CONFIG_SYS_ATA_ALT_OFFSET 0x3f0
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Another important point is that maybe you have to power the pcmcia
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||||
subsystem. This is very board specific, for an example on how to
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do it please search for CONFIG_EXADRON1 in cmd_pcmcia.c
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31
doc/README.commands.spl
Normal file
31
doc/README.commands.spl
Normal file
@@ -0,0 +1,31 @@
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The spl command is used to export a boot parameter image to RAM. Later
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it may implement more functions connected to the SPL.
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SUBCOMMAND EXPORT
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To execute the command everything has to be in place as if bootm should be
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used. (kernel image, initrd-image, fdt-image etc.)
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export has two subcommands:
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atags: exports the ATAGS
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fdt: exports the FDT
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Call is:
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spl export <ftd|atags> [kernel_addr] [initrd_addr] [fdt_addr if fdt]
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|
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TYPICAL CALL
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on OMAP3:
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nandecc hw
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nand read 0x82000000 0x280000 0x400000 /* Read kernel image from NAND*/
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spl export atags /* export ATAGS */
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nand erase 0x680000 0x20000 /* erase - one page */
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nand write 0x80000100 0x680000 0x20000 /* write the image - one page */
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call with FDT:
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nandecc hw
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nand read 0x82000000 0x280000 0x400000 /* Read kernel image from NAND*/
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tftpboot 0x80000100 devkit8000.dtb /* Read fdt */
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spl export fdt 0x82000000 - 0x80000100 /* export FDT */
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nand erase 0x680000 0x20000 /* erase - one page */
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nand write <adress shown by spl export> 0x680000 0x20000
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@@ -7,20 +7,24 @@ i.MX6q SabreLite board.
|
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---------------------------------
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The recent mainline U-Boot for the Freescale i.MX6q SabreLite board supports
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boot from SD card only. However, by default, the early version of SabreLite
|
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boot from SD card only. However, by default, the SabreLite
|
||||
boards boot from the SPI NOR flash. These boards need to be reflashed with
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a small SD card loader to support boot from SD card. This small SD card loader
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will be flashed into the SPI NOR. The board will still boot from SPI NOR, but
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the loader will in turn request the BootROM to load the U-Boot from SD card.
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At the moment of writing, please check with Freescale on the availablity of
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this small SD loader binary.
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|
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The SD card loader is available from
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https://wiki.linaro.org/Boards/MX6QSabreLite
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|
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under a open-source 3-clause BSD license.
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|
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To update the SPI-NOR on the SabreLite board without the Freescale
|
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manufacturing tool use the following procedure:
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1. Write this SD card loader onto a large SD card using:
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sudo dd if=MX6_SPI_to_SD_loader.bin of=/dev/sXx
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sudo dd if=iMX6DQ_SPI_to_uSDHC3.bin of=/dev/sXx
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|
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Note: Replace sXx with the device representing the SD card in your system.
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|
||||
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||||
74
doc/SPL/README.omap3
Normal file
74
doc/SPL/README.omap3
Normal file
@@ -0,0 +1,74 @@
|
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Overview of SPL on OMAP3 devices
|
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================================
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Introduction
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------------
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This document provides an overview of how SPL functions on OMAP3 (and related
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such as am35x and am37x) processors.
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Methodology
|
||||
-----------
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|
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On these platforms the ROM supports trying a sequence of boot devices. Once
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||||
one has been used successfully to load SPL this information is stored in memory
|
||||
and the location stored in a register. We will read this to determine where to
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||||
read U-Boot from in turn.
|
||||
|
||||
Memory Map
|
||||
----------
|
||||
|
||||
This is an example of a typical setup. See top-level README for documentation
|
||||
of which CONFIG variables control these values. For a given board and the
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||||
amount of DRAM available to it different values may need to be used.
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||||
Note that the size of the SPL text rodata and data is enforced with a CONFIG
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||||
option and growing over that size results in a link error. The SPL stack
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||||
starts at the top of SRAM (which is configurable) and grows downward. The
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space between the top of SRAM and the enforced upper bound on the size of the
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SPL text, data and rodata is considered the safe stack area. Details on
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||||
confirming this behavior are shown below.
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|
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A portion of the system memory map looks as follows:
|
||||
SRAM: 0x40200000 - 0x4020FFFF
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||||
DDR1: 0x80000000 - 0xBFFFFFFF
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||||
|
||||
Option 1 (SPL only):
|
||||
0x40200800 - 0x4020BBFF: Area for SPL text, data and rodata
|
||||
0x4020BC00 - 0x4020FFFC: Area for the SPL stack.
|
||||
0x80000000 - 0x8007FFFF: Area for the SPL BSS.
|
||||
0x80100000: CONFIG_SYS_TEXT_BASE of U-Boot
|
||||
0x80208000 - 0x80307FFF: malloc() pool available to SPL.
|
||||
|
||||
Option 2 (SPL or X-Loader):
|
||||
0x40200800 - 0x4020BBFF: Area for SPL text, data and rodata
|
||||
0x4020BC00 - 0x4020FFFC: Area for the SPL stack.
|
||||
0x80008000: CONFIG_SYS_TEXT_BASE of U-Boot
|
||||
0x87000000 - 0x8707FFFF: Area for the SPL BSS.
|
||||
0x87080000 - 0x870FFFFF: malloc() pool available to SPL.
|
||||
|
||||
For the areas that reside within DDR1 they must not be used prior to s_init()
|
||||
completing. Note that CONFIG_SYS_TEXT_BASE must be clear of the areas that SPL
|
||||
uses while running. This is why we have two versions of the memory map that
|
||||
only vary in where the BSS and malloc pool reside.
|
||||
|
||||
Estimating stack usage
|
||||
----------------------
|
||||
|
||||
With gcc 4.6 (and later) and the use of GNU cflow it is possible to estimate
|
||||
stack usage at various points in run sequence of SPL. The -fstack-usage option
|
||||
to gcc will produce '.su' files (such as arch/arm/cpu/armv7/syslib.su) that
|
||||
will give stack usage information and cflow can construct program flow.
|
||||
|
||||
Must have gcc 4.6 or later, which supports -fstack-usage
|
||||
|
||||
1) Build normally
|
||||
2) Perform the following shell command to generate a list of C files used in
|
||||
SPL:
|
||||
$ find spl -name '*.su' | sed -e 's:^spl/::' -e 's:[.]su$:.c:' > used-spl.list
|
||||
3) Execute cflow:
|
||||
$ cflow --main=board_init_r `cat used-spl.list` 2>&1 | $PAGER
|
||||
|
||||
cflow will spit out a number of warnings as it does not parse
|
||||
the config files and picks functions based on #ifdef. Parsing the '.i'
|
||||
files instead introduces another set of headaches. These warnings are
|
||||
not usually important to understanding the flow, however.
|
||||
17
doc/device-tree-bindings/README
Normal file
17
doc/device-tree-bindings/README
Normal file
@@ -0,0 +1,17 @@
|
||||
Device Tree Bindings Staging Area
|
||||
=================================
|
||||
|
||||
This directory contains device tree bindings for U-Boot.
|
||||
|
||||
These follow along with Linux kernel bindings, with a few additions. By
|
||||
adding the files here, U-Boot patches can clearly show thees additions.
|
||||
This makes it easier for device tree people to review these additions in
|
||||
patches sent to the U-Boot mailing list.
|
||||
|
||||
The intent IS to commit these files to U-Boot. Hopefully at some point
|
||||
the files will be stored in another repo (shared with Linux) which is
|
||||
brought in as needed. Changes here are intended to mirror changes in the
|
||||
Linux Documentation/devicetree/bindings/ directory.
|
||||
|
||||
sjg@chromium.org
|
||||
17-Jan-12
|
||||
207
doc/device-tree-bindings/clock/nvidia,tegra20-car.txt
Normal file
207
doc/device-tree-bindings/clock/nvidia,tegra20-car.txt
Normal file
@@ -0,0 +1,207 @@
|
||||
NVIDIA Tegra20 Clock And Reset Controller
|
||||
|
||||
This binding uses the common clock binding:
|
||||
Documentation/devicetree/bindings/clock/clock-bindings.txt
|
||||
|
||||
The CAR (Clock And Reset) Controller on Tegra is the HW module responsible
|
||||
for muxing and gating Tegra's clocks, and setting their rates.
|
||||
|
||||
Required properties :
|
||||
- compatible : Should be "nvidia,tegra20-car"
|
||||
- reg : Should contain CAR registers location and length
|
||||
- clocks : Should contain phandle and clock specifiers for two clocks:
|
||||
the 32 KHz "32k_in", and the board-specific oscillator "osc".
|
||||
- #clock-cells : Should be 1.
|
||||
In clock consumers, this cell represents the clock ID exposed by the CAR.
|
||||
|
||||
The first 96 clocks are numbered to match the bits in the CAR's CLK_OUT_ENB
|
||||
registers. These IDs often match those in the CAR's RST_DEVICES registers,
|
||||
but not in all cases. Some bits in CLK_OUT_ENB affect multiple clocks. In
|
||||
this case, those clocks are assigned IDs above 95 in order to highlight
|
||||
this issue. Implementations that interpret these clock IDs as bit values
|
||||
within the CLK_OUT_ENB or RST_DEVICES registers should be careful to
|
||||
explicitly handle these special cases.
|
||||
|
||||
The balance of the clocks controlled by the CAR are assigned IDs of 96 and
|
||||
above.
|
||||
|
||||
0 cpu
|
||||
1 unassigned
|
||||
2 unassigned
|
||||
3 ac97
|
||||
4 rtc
|
||||
5 tmr
|
||||
6 uart1
|
||||
7 unassigned (register bit affects uart2 and vfir)
|
||||
8 gpio
|
||||
9 sdmmc2
|
||||
10 unassigned (register bit affects spdif_in and spdif_out)
|
||||
11 i2s1
|
||||
12 i2c1
|
||||
13 ndflash
|
||||
14 sdmmc1
|
||||
15 sdmmc4
|
||||
16 twc
|
||||
17 pwm
|
||||
18 i2s2
|
||||
19 epp
|
||||
20 unassigned (register bit affects vi and vi_sensor)
|
||||
21 2d
|
||||
22 usbd
|
||||
23 isp
|
||||
24 3d
|
||||
25 ide
|
||||
26 disp2
|
||||
27 disp1
|
||||
28 host1x
|
||||
29 vcp
|
||||
30 unassigned
|
||||
31 cache2
|
||||
|
||||
32 mem
|
||||
33 ahbdma
|
||||
34 apbdma
|
||||
35 unassigned
|
||||
36 kbc
|
||||
37 stat_mon
|
||||
38 pmc
|
||||
39 fuse
|
||||
40 kfuse
|
||||
41 sbc1
|
||||
42 snor
|
||||
43 spi1
|
||||
44 sbc2
|
||||
45 xio
|
||||
46 sbc3
|
||||
47 dvc
|
||||
48 dsi
|
||||
49 unassigned (register bit affects tvo and cve)
|
||||
50 mipi
|
||||
51 hdmi
|
||||
52 csi
|
||||
53 tvdac
|
||||
54 i2c2
|
||||
55 uart3
|
||||
56 unassigned
|
||||
57 emc
|
||||
58 usb2
|
||||
59 usb3
|
||||
60 mpe
|
||||
61 vde
|
||||
62 bsea
|
||||
63 bsev
|
||||
|
||||
64 speedo
|
||||
65 uart4
|
||||
66 uart5
|
||||
67 i2c3
|
||||
68 sbc4
|
||||
69 sdmmc3
|
||||
70 pcie
|
||||
71 owr
|
||||
72 afi
|
||||
73 csite
|
||||
74 unassigned
|
||||
75 avpucq
|
||||
76 la
|
||||
77 unassigned
|
||||
78 unassigned
|
||||
79 unassigned
|
||||
80 unassigned
|
||||
81 unassigned
|
||||
82 unassigned
|
||||
83 unassigned
|
||||
84 irama
|
||||
85 iramb
|
||||
86 iramc
|
||||
87 iramd
|
||||
88 cram2
|
||||
89 audio_2x a/k/a audio_2x_sync_clk
|
||||
90 clk_d
|
||||
91 unassigned
|
||||
92 sus
|
||||
93 cdev1
|
||||
94 cdev2
|
||||
95 unassigned
|
||||
|
||||
96 uart2
|
||||
97 vfir
|
||||
98 spdif_in
|
||||
99 spdif_out
|
||||
100 vi
|
||||
101 vi_sensor
|
||||
102 tvo
|
||||
103 cve
|
||||
104 osc
|
||||
105 clk_32k a/k/a clk_s
|
||||
106 clk_m
|
||||
107 sclk
|
||||
108 cclk
|
||||
109 hclk
|
||||
110 pclk
|
||||
111 blink
|
||||
112 pll_a
|
||||
113 pll_a_out0
|
||||
114 pll_c
|
||||
115 pll_c_out1
|
||||
116 pll_d
|
||||
117 pll_d_out0
|
||||
118 pll_e
|
||||
119 pll_m
|
||||
120 pll_m_out1
|
||||
121 pll_p
|
||||
122 pll_p_out1
|
||||
123 pll_p_out2
|
||||
124 pll_p_out3
|
||||
125 pll_p_out4
|
||||
126 pll_s
|
||||
127 pll_u
|
||||
128 pll_x
|
||||
129 cop a/k/a avp
|
||||
130 audio a/k/a audio_sync_clk
|
||||
|
||||
Example SoC include file:
|
||||
|
||||
/ {
|
||||
tegra_car: clock@60006000 {
|
||||
compatible = "nvidia,tegra20-car";
|
||||
reg = <0x60006000 0x1000>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
usb@c5004000 {
|
||||
clocks = <&tegra_car 58>; /* usb2 */
|
||||
};
|
||||
};
|
||||
|
||||
Example board file:
|
||||
|
||||
/ {
|
||||
clocks {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
osc: clock {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <12000000>;
|
||||
};
|
||||
};
|
||||
|
||||
i2c@7000d000 {
|
||||
pmic@34 {
|
||||
compatible = "ti,tps6586x";
|
||||
reg = <0x34>;
|
||||
|
||||
clk_32k: clock {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <32768>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&tegra_car {
|
||||
clocks = <&clk_32k> <&osc>;
|
||||
};
|
||||
};
|
||||
23
doc/device-tree-bindings/i2c/tegra20-i2c.txt
Normal file
23
doc/device-tree-bindings/i2c/tegra20-i2c.txt
Normal file
@@ -0,0 +1,23 @@
|
||||
(Placeholder note while we locate the kernel Tegra20 bindings)
|
||||
|
||||
Added in U-Boot:
|
||||
|
||||
Required properties:
|
||||
- clocks : Two clocks must be given, each as a phandle to the Tegra's
|
||||
CAR node and the clock number as a parameter:
|
||||
- the I2C clock to use for the peripheral
|
||||
- the pll_p_out3 clock, which can be used for fast operation. This
|
||||
does not change and is the same for all I2C nodes.
|
||||
|
||||
Example:
|
||||
(TODO: merge with existing example):
|
||||
|
||||
i2c@7000c400 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "nvidia,tegra20-i2c";
|
||||
reg = <0x7000C400 0x100>;
|
||||
interrupts = < 116 >;
|
||||
/* PERIPH_ID_I2C2, PLL_P_OUT3 */
|
||||
clocks = <&tegra_car 54>, <&tegra_car 124>;
|
||||
};
|
||||
25
doc/device-tree-bindings/usb/tegra-usb.txt
Normal file
25
doc/device-tree-bindings/usb/tegra-usb.txt
Normal file
@@ -0,0 +1,25 @@
|
||||
Tegra SOC USB controllers
|
||||
|
||||
The device node for a USB controller that is part of a Tegra
|
||||
SOC is as described in the document "Open Firmware Recommended
|
||||
Practice : Universal Serial Bus" with the following modifications
|
||||
and additions :
|
||||
|
||||
Required properties :
|
||||
- compatible : Should be "nvidia,tegra20-ehci" for USB controllers
|
||||
used in host mode.
|
||||
- phy_type : Should be one of "ulpi" or "utmi".
|
||||
- nvidia,vbus-gpio : If present, specifies a gpio that needs to be
|
||||
activated for the bus to be powered.
|
||||
|
||||
Optional properties:
|
||||
- dr_mode : dual role mode. Indicates the working mode for
|
||||
nvidia,tegra20-ehci compatible controllers. Can be "host", "peripheral",
|
||||
or "otg". Default to "host" if not defined for backward compatibility.
|
||||
host means this is a host controller
|
||||
peripheral means it is device controller
|
||||
otg means it can operate as either ("on the go")
|
||||
- nvidia,has-legacy-mode : boolean indicates whether this controller can
|
||||
operate in legacy mode (as APX 2500 / 2600). In legacy mode some
|
||||
registers are accessed through the APB_MISC base address instead of
|
||||
the USB controller.
|
||||
Reference in New Issue
Block a user