yair/u-boot-tk1-som
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

Merge branch 'master' of git://www.denx.de/git/u-boot-mmc

Browse Source
This commit is contained in:
Tom Rini
2012-10-22 16:53:19 -07:00
parent bcf28c23f2 757bff49ba
commit bdc3ff6e4f
24 changed files with 843 additions and 760 deletions
Download Patch File Download Diff File Expand all files Collapse all files

87
include/bouncebuf.h Normal file
View File

@@ -0,0 +1,87 @@
/*
* Generic bounce buffer implementation
*
* Copyright (C) 2012 Marek Vasut <marex@denx.de>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef __INCLUDE_BOUNCEBUF_H__
#define __INCLUDE_BOUNCEBUF_H__
/*
* GEN_BB_READ -- Data are read from the buffer eg. by DMA hardware.
* The source buffer is copied into the bounce buffer (if unaligned, otherwise
* the source buffer is used directly) upon start() call, then the operation
* requiring the aligned transfer happens, then the bounce buffer is lost upon
* stop() call.
*/
#define GEN_BB_READ (1 << 0)
/*
* GEN_BB_WRITE -- Data are written into the buffer eg. by DMA hardware.
* The source buffer starts in an undefined state upon start() call, then the
* operation requiring the aligned transfer happens, then the bounce buffer is
* copied into the destination buffer (if unaligned, otherwise destination
* buffer is used directly) upon stop() call.
*/
#define GEN_BB_WRITE (1 << 1)
/*
* GEN_BB_RW -- Data are read and written into the buffer eg. by DMA hardware.
* The source buffer is copied into the bounce buffer (if unaligned, otherwise
* the source buffer is used directly) upon start() call, then the operation
* requiring the aligned transfer happens, then the bounce buffer is copied
* into the destination buffer (if unaligned, otherwise destination buffer is
* used directly) upon stop() call.
*/
#define GEN_BB_RW (GEN_BB_READ | GEN_BB_WRITE)
#ifdef CONFIG_BOUNCE_BUFFER
/**
* bounce_buffer_start() -- Start the bounce buffer session
* data: pointer to buffer to be aligned
* len: length of the buffer
* backup: pointer to backup buffer (the original value is stored here if
* needed
* flags: flags describing the transaction, see above.
*/
int bounce_buffer_start(void **data, size_t len, void **backup, uint8_t flags);
/**
* bounce_buffer_stop() -- Finish the bounce buffer session
* data: pointer to buffer that was aligned
* len: length of the buffer
* backup: pointer to backup buffer (the original value is stored here if
* needed
* flags: flags describing the transaction, see above.
*/
int bounce_buffer_stop(void **data, size_t len, void **backup, uint8_t flags);
#else
static inline int bounce_buffer_start(void **data, size_t len, void **backup,
uint8_t flags)
{
return 0;
}
static inline int bounce_buffer_stop(void **data, size_t len, void **backup,
uint8_t flags)
{
return 0;
}
#endif
#endif

2
include/configs/apx4devkit.h
View File

@@ -132,7 +132,7 @@
#ifdef CONFIG_CMD_MMC
#define CONFIG_MMC
#define CONFIG_GENERIC_MMC
#define CONFIG_MMC_BOUNCE_BUFFER
#define CONFIG_BOUNCE_BUFFER
#define CONFIG_MXS_MMC
#endif

3
include/configs/lubbock.h
View File

@@ -130,7 +130,8 @@
#define CONFIG_SYS_CPUSPEED 0x161 /* set core clock to 400/200/100 MHz */
#ifdef CONFIG_MMC
#define CONFIG_PXA_MMC
#define CONFIG_GENERIC_MMC
#define CONFIG_PXA_MMC_GENERIC
#define CONFIG_CMD_MMC
#define CONFIG_SYS_MMC_BASE 0xF0000000
#endif

2
include/configs/m28evk.h
View File

@@ -135,7 +135,7 @@
*/
#ifdef CONFIG_CMD_MMC
#define CONFIG_MMC
#define CONFIG_MMC_BOUNCE_BUFFER
#define CONFIG_BOUNCE_BUFFER
#define CONFIG_GENERIC_MMC
#define CONFIG_MXS_MMC
#endif

2
include/configs/mx28evk.h
View File

@@ -142,7 +142,7 @@
#ifdef CONFIG_CMD_MMC
#define CONFIG_MMC
#define CONFIG_GENERIC_MMC
#define CONFIG_MMC_BOUNCE_BUFFER
#define CONFIG_BOUNCE_BUFFER
#define CONFIG_MXS_MMC
#endif

3
include/configs/palmtc.h
View File

@@ -77,7 +77,8 @@
*/
#ifdef CONFIG_CMD_MMC
#define CONFIG_MMC
#define CONFIG_PXA_MMC
#define CONFIG_GENERIC_MMC
#define CONFIG_PXA_MMC_GENERIC
#define CONFIG_SYS_MMC_BASE 0xF0000000
#define CONFIG_CMD_FAT
#define CONFIG_CMD_EXT2

3
include/configs/pxa255_idp.h
View File

@@ -245,7 +245,8 @@
#define RTC 1 /* enable 32KHz osc */
#ifdef CONFIG_MMC
#define CONFIG_PXA_MMC
#define CONFIG_GENERIC_MMC
#define CONFIG_PXA_MMC_GENERIC
#define CONFIG_CMD_MMC
#define CONFIG_SYS_MMC_BASE 0xF0000000
#endif

3
include/configs/trizepsiv.h
View File

@@ -170,7 +170,8 @@
#define CONFIG_SYS_CPUSPEED 0x207 /* need to look more closely, I think this is Turbo = 2x, L=91Mhz */
#ifdef CONFIG_MMC
#define CONFIG_PXA_MMC
#define CONFIG_GENERIC_MMC
#define CONFIG_PXA_MMC_GENERIC
#define CONFIG_CMD_MMC
#define CONFIG_SYS_MMC_BASE 0xF0000000
#endif

191
include/dwmmc.h Normal file
View File

@@ -0,0 +1,191 @@
/*
* (C) Copyright 2012 SAMSUNG Electronics
* Jaehoon Chung <jh80.chung@samsung.com>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*
*/
#ifndef __DWMMC_HW_H
#define __DWMMC_HW_H
#include <asm/io.h>
#include <mmc.h>
#define DWMCI_CTRL 0x000
#define DWMCI_PWREN 0x004
#define DWMCI_CLKDIV 0x008
#define DWMCI_CLKSRC 0x00C
#define DWMCI_CLKENA 0x010
#define DWMCI_TMOUT 0x014
#define DWMCI_CTYPE 0x018
#define DWMCI_BLKSIZ 0x01C
#define DWMCI_BYTCNT 0x020
#define DWMCI_INTMASK 0x024
#define DWMCI_CMDARG 0x028
#define DWMCI_CMD 0x02C
#define DWMCI_RESP0 0x030
#define DWMCI_RESP1 0x034
#define DWMCI_RESP2 0x038
#define DWMCI_RESP3 0x03C
#define DWMCI_MINTSTS 0x040
#define DWMCI_RINTSTS 0x044
#define DWMCI_STATUS 0x048
#define DWMCI_FIFOTH 0x04C
#define DWMCI_CDETECT 0x050
#define DWMCI_WRTPRT 0x054
#define DWMCI_GPIO 0x058
#define DWMCI_TCMCNT 0x05C
#define DWMCI_TBBCNT 0x060
#define DWMCI_DEBNCE 0x064
#define DWMCI_USRID 0x068
#define DWMCI_VERID 0x06C
#define DWMCI_HCON 0x070
#define DWMCI_UHS_REG 0x074
#define DWMCI_BMOD 0x080
#define DWMCI_PLDMND 0x084
#define DWMCI_DBADDR 0x088
#define DWMCI_IDSTS 0x08C
#define DWMCI_IDINTEN 0x090
#define DWMCI_DSCADDR 0x094
#define DWMCI_BUFADDR 0x098
#define DWMCI_DATA 0x200
/* Interrupt Mask register */
#define DWMCI_INTMSK_ALL 0xffffffff
#define DWMCI_INTMSK_RE (1 << 1)
#define DWMCI_INTMSK_CDONE (1 << 2)
#define DWMCI_INTMSK_DTO (1 << 3)
#define DWMCI_INTMSK_TXDR (1 << 4)
#define DWMCI_INTMSK_RXDR (1 << 5)
#define DWMCI_INTMSK_DCRC (1 << 7)
#define DWMCI_INTMSK_RTO (1 << 8)
#define DWMCI_INTMSK_DRTO (1 << 9)
#define DWMCI_INTMSK_HTO (1 << 10)
#define DWMCI_INTMSK_FRUN (1 << 11)
#define DWMCI_INTMSK_HLE (1 << 12)
#define DWMCI_INTMSK_SBE (1 << 13)
#define DWMCI_INTMSK_ACD (1 << 14)
#define DWMCI_INTMSK_EBE (1 << 15)
/* Raw interrupt Regsiter */
#define DWMCI_DATA_ERR (DWMCI_INTMSK_EBE | DWMCI_INTMSK_SBE | DWMCI_INTMSK_HLE |\
DWMCI_INTMSK_FRUN | DWMCI_INTMSK_EBE | DWMCI_INTMSK_DCRC)
#define DWMCI_DATA_TOUT (DWMCI_INTMSK_HTO | DWMCI_INTMSK_DRTO)
/* CTRL register */
#define DWMCI_CTRL_RESET (1 << 0)
#define DWMCI_CTRL_FIFO_RESET (1 << 1)
#define DWMCI_CTRL_DMA_RESET (1 << 2)
#define DWMCI_DMA_EN (1 << 5)
#define DWMCI_CTRL_SEND_AS_CCSD (1 << 10)
#define DWMCI_IDMAC_EN (1 << 25)
#define DWMCI_RESET_ALL (DWMCI_CTRL_RESET | DWMCI_CTRL_FIFO_RESET |\
DWMCI_CTRL_DMA_RESET)
/* CMD register */
#define DWMCI_CMD_RESP_EXP (1 << 6)
#define DWMCI_CMD_RESP_LENGTH (1 << 7)
#define DWMCI_CMD_CHECK_CRC (1 << 8)
#define DWMCI_CMD_DATA_EXP (1 << 9)
#define DWMCI_CMD_RW (1 << 10)
#define DWMCI_CMD_SEND_STOP (1 << 12)
#define DWMCI_CMD_ABORT_STOP (1 << 14)
#define DWMCI_CMD_PRV_DAT_WAIT (1 << 13)
#define DWMCI_CMD_UPD_CLK (1 << 21)
#define DWMCI_CMD_USE_HOLD_REG (1 << 29)
#define DWMCI_CMD_START (1 << 31)
/* CLKENA register */
#define DWMCI_CLKEN_ENABLE (1 << 0)
#define DWMCI_CLKEN_LOW_PWR (1 << 16)
/* Card-type registe */
#define DWMCI_CTYPE_1BIT 0
#define DWMCI_CTYPE_4BIT (1 << 0)
#define DWMCI_CTYPE_8BIT (1 << 16)
/* Status Register */
#define DWMCI_BUSY (1 << 9)
/* FIFOTH Register */
#define MSIZE(x) ((x) << 28)
#define RX_WMARK(x) ((x) << 16)
#define TX_WMARK(x) (x)
#define DWMCI_IDMAC_OWN (1 << 31)
#define DWMCI_IDMAC_CH (1 << 4)
#define DWMCI_IDMAC_FS (1 << 3)
#define DWMCI_IDMAC_LD (1 << 2)
/* Bus Mode Register */
#define DWMCI_BMOD_IDMAC_RESET (1 << 0)
#define DWMCI_BMOD_IDMAC_FB (1 << 1)
#define DWMCI_BMOD_IDMAC_EN (1 << 7)
struct dwmci_host {
char *name;
void *ioaddr;
unsigned int quirks;
unsigned int caps;
unsigned int version;
unsigned int clock;
unsigned int bus_hz;
int dev_index;
int buswidth;
u32 fifoth_val;
struct mmc *mmc;
void (*clksel)(struct dwmci_host *host);
unsigned int (*mmc_clk)(int dev_index);
};
struct dwmci_idmac {
u32 flags;
u32 cnt;
u32 addr;
u32 next_addr;
};
static inline void dwmci_writel(struct dwmci_host *host, int reg, u32 val)
{
writel(val, host->ioaddr + reg);
}
static inline void dwmci_writew(struct dwmci_host *host, int reg, u16 val)
{
writew(val, host->ioaddr + reg);
}
static inline void dwmci_writeb(struct dwmci_host *host, int reg, u8 val)
{
writeb(val, host->ioaddr + reg);
}
static inline u32 dwmci_readl(struct dwmci_host *host, int reg)
{
return readl(host->ioaddr + reg);
}
static inline u16 dwmci_readw(struct dwmci_host *host, int reg)
{
return readw(host->ioaddr + reg);
}
static inline u8 dwmci_readb(struct dwmci_host *host, int reg)
{
return readb(host->ioaddr + reg);
}
int add_dwmci(struct dwmci_host *host, u32 max_clk, u32 min_clk);
#endif /* __DWMMC_HW_H */

1
include/sdhci.h
View File

@@ -224,6 +224,7 @@
#define SDHCI_QUIRK_NO_HISPD_BIT (1 << 3)
#define SDHCI_QUIRK_BROKEN_VOLTAGE (1 << 4)
#define SDHCI_QUIRK_NO_CD (1 << 5)
#define SDHCI_QUIRK_WAIT_SEND_CMD (1 << 6)
/* to make gcc happy */
struct sdhci_host;