Blackfin: bf537-pnav: new board port
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
This commit is contained in:
Mike Frysinger
172
include/configs/bf537-pnav.h
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172
include/configs/bf537-pnav.h
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/*
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* U-boot - Configuration file for BF537 PNAV board
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*/
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#ifndef __CONFIG_BF537_PNAV_H__
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#define __CONFIG_BF537_PNAV_H__
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#include <asm/blackfin-config-pre.h>
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/*
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* Processor Settings
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*/
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#define CONFIG_BFIN_CPU bf537-0.2
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#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_SPI_MASTER
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/*
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* Clock Settings
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* CCLK = (CLKIN * VCO_MULT) / CCLK_DIV
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* SCLK = (CLKIN * VCO_MULT) / SCLK_DIV
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*/
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/* CONFIG_CLKIN_HZ is any value in Hz */
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#define CONFIG_CLKIN_HZ 24576000
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/* CLKIN_HALF controls the DF bit in PLL_CTL 0 = CLKIN */
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/* 1 = CLKIN / 2 */
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#define CONFIG_CLKIN_HALF 0
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/* PLL_BYPASS controls the BYPASS bit in PLL_CTL 0 = do not bypass */
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/* 1 = bypass PLL */
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#define CONFIG_PLL_BYPASS 0
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/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL */
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/* Values can range from 0-63 (where 0 means 64) */
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#define CONFIG_VCO_MULT 20
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/* CCLK_DIV controls the core clock divider */
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/* Values can be 1, 2, 4, or 8 ONLY */
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#define CONFIG_CCLK_DIV 1
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/* SCLK_DIV controls the system clock divider */
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/* Values can range from 1-15 */
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#define CONFIG_SCLK_DIV 4
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/*
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* Memory Settings
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*/
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#define CONFIG_MEM_ADD_WDTH 10
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#define CONFIG_MEM_SIZE 64
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#define CONFIG_EBIU_SDRRC_VAL 0x3b7
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#define CONFIG_EBIU_SDGCTL_VAL 0x9111cd
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#define CONFIG_EBIU_AMGCTL_VAL 0xFF
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#define CONFIG_EBIU_AMBCTL0_VAL 0x7BB033B0
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#define CONFIG_EBIU_AMBCTL1_VAL 0xFFC27BB0
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#define CONFIG_SYS_MONITOR_LEN (256 * 1024)
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#define CONFIG_SYS_MALLOC_LEN (128 * 1024)
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/*
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* Network Settings
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*/
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#ifndef __ADSPBF534__
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#define ADI_CMDS_NETWORK 1
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#define CONFIG_BFIN_MAC
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#define CONFIG_RMII
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#define CONFIG_NET_MULTI 1
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#endif
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#define CONFIG_HOSTNAME bf537-pnav
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/* Uncomment next line to use fixed MAC address */
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/* #define CONFIG_ETHADDR 02:80:ad:24:21:18 */
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/*
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* Flash Settings
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*/
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#define CONFIG_FLASH_CFI_DRIVER
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#define CONFIG_SYS_FLASH_BASE 0x20000000
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#define CONFIG_SYS_FLASH_CFI
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#define CONFIG_SYS_MAX_FLASH_BANKS 1
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#define CONFIG_SYS_MAX_FLASH_SECT 71
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/*
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* SPI Settings
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*/
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#define CONFIG_BFIN_SPI
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#define CONFIG_ENV_SPI_MAX_HZ 30000000
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#define CONFIG_SF_DEFAULT_HZ 30000000
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#define CONFIG_SPI_FLASH
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#define CONFIG_SPI_FLASH_STMICRO
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/*
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* Env Storage Settings
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*/
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#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_SPI_MASTER)
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#define ENV_IS_EMBEDDED_CUSTOM
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#define CONFIG_ENV_IS_IN_SPI_FLASH
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#define CONFIG_ENV_OFFSET 0x4000
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#else
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#define ENV_IS_EMBEDDED
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#define CONFIG_ENV_IS_IN_FLASH 1
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#define CONFIG_ENV_ADDR 0x20004000
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#define CONFIG_ENV_OFFSET 0x4000
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#endif
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#define CONFIG_ENV_SIZE 0x1000
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#define CONFIG_ENV_SECT_SIZE 0x2000
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/*
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* NAND Settings
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*/
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#define CONFIG_NAND_PLAT
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#define CONFIG_SYS_NAND_BASE 0x20100000
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#define CONFIG_SYS_MAX_NAND_DEVICE 1
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#define BFIN_NAND_CLE(chip) ((unsigned long)(chip)->IO_ADDR_W | (1 << 2))
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#define BFIN_NAND_ALE(chip) ((unsigned long)(chip)->IO_ADDR_W | (1 << 1))
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#define BFIN_NAND_READY PF12
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#define BFIN_NAND_WRITE(addr, cmd) \
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do { \
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bfin_write8(addr, cmd); \
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SSYNC(); \
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} while (0)
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#define NAND_PLAT_WRITE_CMD(chip, cmd) BFIN_NAND_WRITE(BFIN_NAND_CLE(chip), cmd)
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#define NAND_PLAT_WRITE_ADR(chip, cmd) BFIN_NAND_WRITE(BFIN_NAND_ALE(chip), cmd)
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#define NAND_PLAT_DEV_READY(chip) (bfin_read_PORTHIO() & BFIN_NAND_READY)
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#define NAND_PLAT_INIT() \
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do { \
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bfin_write_PORTH_FER(bfin_read_PORTH_FER() & ~BFIN_NAND_READY); \
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bfin_write_PORTHIO_DIR(bfin_read_PORTHIO_DIR() & ~BFIN_NAND_READY); \
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bfin_write_PORTHIO_INEN(bfin_read_PORTHIO_INEN() | BFIN_NAND_READY); \
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} while (0)
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/*
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* I2C settings
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*/
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#define CONFIG_BFIN_TWI_I2C 1
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#define CONFIG_HARD_I2C 1
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#define CONFIG_SYS_I2C_SPEED 50000
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#define CONFIG_SYS_I2C_SLAVE 0
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/*
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* Misc Settings
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*/
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#define CONFIG_BAUDRATE 115200
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#define CONFIG_MISC_INIT_R
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#define CONFIG_RTC_BFIN
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#define CONFIG_UART_CONSOLE 0
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/* JFFS Partition offset set */
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#define CONFIG_SYS_JFFS2_FIRST_BANK 0
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#define CONFIG_SYS_JFFS2_NUM_BANKS 1
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/* 512k reserved for u-boot */
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#define CONFIG_SYS_JFFS2_FIRST_SECTOR 15
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#define CONFIG_BOOTCOMMAND "run nandboot"
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#define CONFIG_BOOTARGS_ROOT "/dev/mtdblock1 rw rootfstype=yaffs"
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/*
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* Pull in common ADI header for remaining command/environment setup
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*/
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#include <configs/bfin_adi_common.h>
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#include <asm/blackfin-config-post.h>
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#endif
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