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Merge branch 'master' of git://git.denx.de/u-boot-spi

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Tom Rini
2015-04-28 07:28:43 -04:00
parent 86e6f7eaa1 c650ca7b4c
commit cc555bd4f4
14 changed files with 93 additions and 94 deletions
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11
README
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@@ -3096,17 +3096,6 @@ CBFS (Coreboot Filesystem) support
memories can be connected with a given cs line.
Currently Xilinx Zynq qspi supports these type of connections.
CONFIG_SYS_SPI_ST_ENABLE_WP_PIN
enable the W#/Vpp signal to disable writing to the status
register on ST MICRON flashes like the N25Q128.
The status register write enable/disable bit, combined with
the W#/VPP signal provides hardware data protection for the
device as follows: When the enable/disable bit is set to 1,
and the W#/VPP signal is driven LOW, the status register
nonvolatile bits become read-only and the WRITE STATUS REGISTER
operation will not execute. The only way to exit this
hardware-protected mode is to drive W#/VPP HIGH.
- SystemACE Support:
CONFIG_SYSTEMACE