* Patch by Jon Loeliger, 2005-05-05
Implemented support for MPC8548CDS board.
Added DDR II support based on SPD values for MPC85xx boards.
This roll-up patch also includes bugfies for the previously
published patches:
DDRII CPO, pre eTSEC, 8548 LBIU, Andy's TSEC, eTSEC 3&4 I/O
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@@ -420,6 +420,7 @@
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#define SPRN_MAS4 0x274 /* MMU Assist Register 4 */
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#define SPRN_MAS5 0x275 /* MMU Assist Register 5 */
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#define SPRN_MAS6 0x276 /* MMU Assist Register 6 */
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#define SPRN_MAS7 0x3B0 /* MMU Assist Register 7 */
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#define SPRN_IVOR32 0x210 /* Interrupt Vector Offset Register 32 */
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#define SPRN_IVOR33 0x211 /* Interrupt Vector Offset Register 33 */
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@@ -584,6 +585,7 @@
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#define MAS4 SPRN_MAS4
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#define MAS5 SPRN_MAS5
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#define MAS6 SPRN_MAS6
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#define MAS7 SPRN_MAS7
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/* Device Control Registers */
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@@ -792,6 +794,8 @@
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#define SVR_8560 0x8070
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#define SVR_8555 0x8079
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#define SVR_8541 0x807A
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#define SVR_8548 0x8031
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#define SVR_8548_E 0x8039
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/* I am just adding a single entry for 8260 boards. I think we may be
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