Initial support for MPC8641 HPCN board.
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@@ -264,6 +264,7 @@
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#define SPRN_ICTC 0x3FB /* Instruction Cache Throttling Control Reg */
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#define SPRN_IMISS 0x3D4 /* Instruction TLB Miss Register */
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#define SPRN_IMMR 0x27E /* Internal Memory Map Register */
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#define SPRN_LDSTCR 0x3F8 /* Load/Store Control Register */
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#define SPRN_L2CR 0x3F9 /* Level 2 Cache Control Regsiter */
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#define SPRN_LR 0x008 /* Link Register */
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#define SPRN_MBAR 0x137 /* System memory base address */
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@@ -443,6 +444,11 @@
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#define SPRN_MCSR 0x23c /* Machine Check Syndrome register */
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#define ESR_ST 0x00800000 /* Store Operation */
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#if defined(CONFIG_MPC86xx)
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#define SPRN_MSSCRO 0x3f6
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#endif
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/* Short-hand versions for a number of the above SPRNs */
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#define CTR SPRN_CTR /* Counter Register */
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@@ -501,10 +507,14 @@
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#define ICMP SPRN_ICMP /* Instruction TLB Compare Register */
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#define IMISS SPRN_IMISS /* Instruction TLB Miss Register */
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#define IMMR SPRN_IMMR /* PPC 860/821 Internal Memory Map Register */
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#define LDSTCR SPRN_LDSTCR /* Load/Store Control Register */
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#define L2CR SPRN_L2CR /* PPC 750 L2 control register */
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#define LR SPRN_LR
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#define MBAR SPRN_MBAR /* System memory base address */
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#if defined(CONFIG_E500)
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#if defined(CONFIG_MPC86xx)
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#define MSSCR0 SPRN_MSSCRO
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#endif
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#if defined(CONFIG_E500) || defined(CONFIG_MPC86xx)
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#define PIR SPRN_PIR
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#endif
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#define SVR SPRN_SVR /* System-On-Chip Version Register */
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@@ -538,7 +548,7 @@
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#define CSRR0 SPRN_CSRR0
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#define CSRR1 SPRN_CSRR1
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#define IVPR SPRN_IVPR
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#define USPRG0 SPRN_USPRG0
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#define USPRG0 SPRN_USPRG
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#define SPRG4R SPRN_SPRG4R
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#define SPRG5R SPRN_SPRG5R
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#define SPRG6R SPRN_SPRG6R
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@@ -755,6 +765,8 @@
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#define PVR_85xx_REV1 (PVR_85xx | 0x0010)
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#define PVR_85xx_REV2 (PVR_85xx | 0x0020)
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#define PVR_86xx 0x80040000
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#define PVR_86xx_REV1 (PVR_86xx | 0x0010)
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/*
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* For the 8xx processors, all of them report the same PVR family for
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@@ -808,6 +820,8 @@
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#define SVR_8548 0x8031
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#define SVR_8548_E 0x8039
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#define SVR_8641 0x8090
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#define SVR_8641D 0x8091
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/* I am just adding a single entry for 8260 boards. I think we may be
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* able to combine mbx, fads, rpxlite, bseip, and classic into a single
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