ARM: vf610: Initial integration for Colibri VF50/VF61
This adds initial support for Colibri VF50/VF61 based on Freescale Vybrid SoC. - CPU clocked at 396/500 MHz - DDR3 at 396MHz - for VF50, use PLL2 as memory clock (synchronous mode) - for VF61, use PLL1 as memory clock (asynchronous mode) - Console on UART0 (Colibri UART_A) - Ethernet on FEC1 - PLL5 based RMII clocking (E.g. No external crystal) - UART_A and UART_C I/O muxing - Boot from NAND by default Tested on Colibri VF50/VF61 booting using serial loader over UART. Signed-off-by: Sanchayan Maity <maitysanchayan@gmail.com> Acked-by: Stefan Agner <stefan@agner.ch>
This commit is contained in:
Sanchayan Maity
committed by
Tom Rini
Tom Rini
parent
7a90a1f260
commit
e7b860fa4d
18
board/toradex/colibri_vf/Kconfig
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18
board/toradex/colibri_vf/Kconfig
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@@ -0,0 +1,18 @@
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if TARGET_COLIBRI_VF
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config SYS_CPU
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default "armv7"
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config SYS_BOARD
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default "colibri_vf"
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config SYS_VENDOR
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default "toradex"
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config SYS_SOC
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default "vf610"
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config SYS_CONFIG_NAME
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default "colibri_vf"
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endif
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6
board/toradex/colibri_vf/MAINTAINERS
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6
board/toradex/colibri_vf/MAINTAINERS
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@@ -0,0 +1,6 @@
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Colibri VFxx
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M: Stefan Agner <stefan.agner@toradex.com>
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S: Maintained
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F: board/toradex/colibri_vf/
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F: include/configs/colibri_vf.h
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F: configs/colibri_vf_defconfig
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7
board/toradex/colibri_vf/Makefile
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7
board/toradex/colibri_vf/Makefile
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@@ -0,0 +1,7 @@
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#
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# Copyright 2013 Freescale Semiconductor, Inc.
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#
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# SPDX-License-Identifier: GPL-2.0+
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#
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obj-y := colibri_vf.o
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361
board/toradex/colibri_vf/colibri_vf.c
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361
board/toradex/colibri_vf/colibri_vf.c
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@@ -0,0 +1,361 @@
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/*
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* Copyright 2015 Toradex, Inc.
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*
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* Based on vf610twr.c:
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* Copyright 2013 Freescale Semiconductor, Inc.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <asm/arch/imx-regs.h>
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#include <asm/arch/iomux-vf610.h>
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#include <asm/arch/ddrmc-vf610.h>
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#include <asm/arch/crm_regs.h>
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#include <asm/arch/clock.h>
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#include <mmc.h>
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#include <fsl_esdhc.h>
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#include <miiphy.h>
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#include <netdev.h>
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#include <i2c.h>
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#include <g_dnl.h>
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DECLARE_GLOBAL_DATA_PTR;
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#define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
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PAD_CTL_DSE_25ohm | PAD_CTL_OBE_IBE_ENABLE)
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#define ESDHC_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_HIGH | \
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PAD_CTL_DSE_20ohm | PAD_CTL_OBE_IBE_ENABLE)
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#define ENET_PAD_CTRL (PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_HIGH | \
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PAD_CTL_DSE_50ohm | PAD_CTL_OBE_IBE_ENABLE)
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int dram_init(void)
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{
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static const struct ddr3_jedec_timings timings = {
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.tinit = 5,
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.trst_pwron = 80000,
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.cke_inactive = 200000,
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.wrlat = 5,
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.caslat_lin = 12,
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.trc = 21,
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.trrd = 4,
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.tccd = 4,
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.tfaw = 20,
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.trp = 6,
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.twtr = 4,
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.tras_min = 15,
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.tmrd = 4,
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.trtp = 4,
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.tras_max = 28080,
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.tmod = 12,
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.tckesr = 4,
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.tcke = 3,
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.trcd_int = 6,
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.tdal = 12,
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.tdll = 512,
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.trp_ab = 6,
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.tref = 3120,
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.trfc = 64,
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.tpdex = 3,
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.txpdll = 10,
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.txsnr = 48,
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.txsr = 468,
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.cksrx = 5,
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.cksre = 5,
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.zqcl = 256,
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.zqinit = 512,
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.zqcs = 64,
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.ref_per_zq = 64,
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.aprebit = 10,
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.wlmrd = 40,
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.wldqsen = 25,
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};
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ddrmc_setup_iomux();
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ddrmc_ctrl_init_ddr3(&timings, NULL, 1, 2);
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gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
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return 0;
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}
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static void setup_iomux_uart(void)
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{
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static const iomux_v3_cfg_t uart_pads[] = {
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NEW_PAD_CTRL(VF610_PAD_PTB4__UART1_TX, UART_PAD_CTRL),
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NEW_PAD_CTRL(VF610_PAD_PTB5__UART1_RX, UART_PAD_CTRL),
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NEW_PAD_CTRL(VF610_PAD_PTB10__UART0_TX, UART_PAD_CTRL),
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NEW_PAD_CTRL(VF610_PAD_PTB11__UART0_RX, UART_PAD_CTRL),
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};
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imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
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}
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static void setup_iomux_enet(void)
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{
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static const iomux_v3_cfg_t enet0_pads[] = {
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NEW_PAD_CTRL(VF610_PAD_PTA6__RMII0_CLKOUT, ENET_PAD_CTRL),
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NEW_PAD_CTRL(VF610_PAD_PTC10__RMII1_MDIO, ENET_PAD_CTRL),
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NEW_PAD_CTRL(VF610_PAD_PTC9__RMII1_MDC, ENET_PAD_CTRL),
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NEW_PAD_CTRL(VF610_PAD_PTC11__RMII1_CRS_DV, ENET_PAD_CTRL),
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NEW_PAD_CTRL(VF610_PAD_PTC12__RMII1_RD1, ENET_PAD_CTRL),
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NEW_PAD_CTRL(VF610_PAD_PTC13__RMII1_RD0, ENET_PAD_CTRL),
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NEW_PAD_CTRL(VF610_PAD_PTC14__RMII1_RXER, ENET_PAD_CTRL),
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NEW_PAD_CTRL(VF610_PAD_PTC15__RMII1_TD1, ENET_PAD_CTRL),
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NEW_PAD_CTRL(VF610_PAD_PTC16__RMII1_TD0, ENET_PAD_CTRL),
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NEW_PAD_CTRL(VF610_PAD_PTC17__RMII1_TXEN, ENET_PAD_CTRL),
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};
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imx_iomux_v3_setup_multiple_pads(enet0_pads, ARRAY_SIZE(enet0_pads));
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}
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static void setup_iomux_i2c(void)
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{
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static const iomux_v3_cfg_t i2c0_pads[] = {
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VF610_PAD_PTB14__I2C0_SCL,
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VF610_PAD_PTB15__I2C0_SDA,
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};
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imx_iomux_v3_setup_multiple_pads(i2c0_pads, ARRAY_SIZE(i2c0_pads));
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}
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#ifdef CONFIG_NAND_VF610_NFC
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static void setup_iomux_nfc(void)
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{
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static const iomux_v3_cfg_t nfc_pads[] = {
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VF610_PAD_PTD23__NF_IO7,
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VF610_PAD_PTD22__NF_IO6,
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VF610_PAD_PTD21__NF_IO5,
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VF610_PAD_PTD20__NF_IO4,
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VF610_PAD_PTD19__NF_IO3,
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VF610_PAD_PTD18__NF_IO2,
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VF610_PAD_PTD17__NF_IO1,
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VF610_PAD_PTD16__NF_IO0,
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VF610_PAD_PTB24__NF_WE_B,
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VF610_PAD_PTB25__NF_CE0_B,
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VF610_PAD_PTB27__NF_RE_B,
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VF610_PAD_PTC26__NF_RB_B,
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VF610_PAD_PTC27__NF_ALE,
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VF610_PAD_PTC28__NF_CLE
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};
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imx_iomux_v3_setup_multiple_pads(nfc_pads, ARRAY_SIZE(nfc_pads));
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}
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#endif
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#ifdef CONFIG_FSL_ESDHC
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struct fsl_esdhc_cfg esdhc_cfg[1] = {
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{ESDHC1_BASE_ADDR},
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};
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int board_mmc_getcd(struct mmc *mmc)
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{
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/* eSDHC1 is always present */
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return 1;
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}
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int board_mmc_init(bd_t *bis)
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{
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static const iomux_v3_cfg_t esdhc1_pads[] = {
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NEW_PAD_CTRL(VF610_PAD_PTA24__ESDHC1_CLK, ESDHC_PAD_CTRL),
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NEW_PAD_CTRL(VF610_PAD_PTA25__ESDHC1_CMD, ESDHC_PAD_CTRL),
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NEW_PAD_CTRL(VF610_PAD_PTA26__ESDHC1_DAT0, ESDHC_PAD_CTRL),
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NEW_PAD_CTRL(VF610_PAD_PTA27__ESDHC1_DAT1, ESDHC_PAD_CTRL),
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NEW_PAD_CTRL(VF610_PAD_PTA28__ESDHC1_DAT2, ESDHC_PAD_CTRL),
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NEW_PAD_CTRL(VF610_PAD_PTA29__ESDHC1_DAT3, ESDHC_PAD_CTRL),
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};
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esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
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imx_iomux_v3_setup_multiple_pads(
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esdhc1_pads, ARRAY_SIZE(esdhc1_pads));
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return fsl_esdhc_initialize(bis, &esdhc_cfg[0]);
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}
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#endif
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static inline int is_colibri_vf61(void)
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{
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struct mscm *mscm = (struct mscm *)MSCM_BASE_ADDR;
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/*
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* Detect board type by Level 2 Cache: VF50 don't have any
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* Level 2 Cache.
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*/
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return !!mscm->cpxcfg1;
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}
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static void clock_init(void)
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{
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struct ccm_reg *ccm = (struct ccm_reg *)CCM_BASE_ADDR;
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struct anadig_reg *anadig = (struct anadig_reg *)ANADIG_BASE_ADDR;
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u32 pfd_clk_sel, ddr_clk_sel;
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clrsetbits_le32(&ccm->ccgr0, CCM_REG_CTRL_MASK,
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CCM_CCGR0_UART0_CTRL_MASK);
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clrsetbits_le32(&ccm->ccgr1, CCM_REG_CTRL_MASK,
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CCM_CCGR1_PIT_CTRL_MASK | CCM_CCGR1_WDOGA5_CTRL_MASK);
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clrsetbits_le32(&ccm->ccgr2, CCM_REG_CTRL_MASK,
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CCM_CCGR2_IOMUXC_CTRL_MASK | CCM_CCGR2_PORTA_CTRL_MASK |
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CCM_CCGR2_PORTB_CTRL_MASK | CCM_CCGR2_PORTC_CTRL_MASK |
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CCM_CCGR2_PORTD_CTRL_MASK | CCM_CCGR2_PORTE_CTRL_MASK);
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clrsetbits_le32(&ccm->ccgr3, CCM_REG_CTRL_MASK,
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CCM_CCGR3_ANADIG_CTRL_MASK | CCM_CCGR3_SCSC_CTRL_MASK);
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clrsetbits_le32(&ccm->ccgr4, CCM_REG_CTRL_MASK,
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CCM_CCGR4_WKUP_CTRL_MASK | CCM_CCGR4_CCM_CTRL_MASK |
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CCM_CCGR4_GPC_CTRL_MASK | CCM_CCGR4_I2C0_CTRL_MASK);
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clrsetbits_le32(&ccm->ccgr6, CCM_REG_CTRL_MASK,
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CCM_CCGR6_OCOTP_CTRL_MASK | CCM_CCGR6_DDRMC_CTRL_MASK);
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clrsetbits_le32(&ccm->ccgr7, CCM_REG_CTRL_MASK,
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CCM_CCGR7_SDHC1_CTRL_MASK);
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clrsetbits_le32(&ccm->ccgr9, CCM_REG_CTRL_MASK,
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CCM_CCGR9_FEC0_CTRL_MASK | CCM_CCGR9_FEC1_CTRL_MASK);
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clrsetbits_le32(&ccm->ccgr10, CCM_REG_CTRL_MASK,
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CCM_CCGR10_NFC_CTRL_MASK);
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clrsetbits_le32(&anadig->pll5_ctrl, ANADIG_PLL5_CTRL_BYPASS |
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ANADIG_PLL5_CTRL_POWERDOWN, ANADIG_PLL5_CTRL_ENABLE |
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ANADIG_PLL5_CTRL_DIV_SELECT);
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if (is_colibri_vf61()) {
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clrsetbits_le32(&anadig->pll2_ctrl, ANADIG_PLL5_CTRL_BYPASS |
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ANADIG_PLL2_CTRL_POWERDOWN,
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ANADIG_PLL2_CTRL_ENABLE |
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ANADIG_PLL2_CTRL_DIV_SELECT);
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}
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clrsetbits_le32(&anadig->pll1_ctrl, ANADIG_PLL1_CTRL_POWERDOWN,
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ANADIG_PLL1_CTRL_ENABLE | ANADIG_PLL1_CTRL_DIV_SELECT);
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clrsetbits_le32(&ccm->ccr, CCM_CCR_OSCNT_MASK,
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CCM_CCR_FIRC_EN | CCM_CCR_OSCNT(5));
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/* See "Typical PLL Configuration" */
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if (is_colibri_vf61()) {
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pfd_clk_sel = CCM_CCSR_PLL1_PFD_CLK_SEL(1);
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ddr_clk_sel = CCM_CCSR_DDRC_CLK_SEL(0);
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} else {
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pfd_clk_sel = CCM_CCSR_PLL1_PFD_CLK_SEL(3);
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ddr_clk_sel = CCM_CCSR_DDRC_CLK_SEL(1);
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}
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clrsetbits_le32(&ccm->ccsr, CCM_REG_CTRL_MASK, pfd_clk_sel |
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CCM_CCSR_PLL2_PFD4_EN | CCM_CCSR_PLL2_PFD3_EN |
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CCM_CCSR_PLL2_PFD2_EN | CCM_CCSR_PLL2_PFD1_EN |
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CCM_CCSR_PLL1_PFD4_EN | CCM_CCSR_PLL1_PFD3_EN |
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CCM_CCSR_PLL1_PFD2_EN | CCM_CCSR_PLL1_PFD1_EN |
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ddr_clk_sel | CCM_CCSR_FAST_CLK_SEL(1) |
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CCM_CCSR_SYS_CLK_SEL(4));
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clrsetbits_le32(&ccm->cacrr, CCM_REG_CTRL_MASK,
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CCM_CACRR_IPG_CLK_DIV(1) | CCM_CACRR_BUS_CLK_DIV(2) |
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CCM_CACRR_ARM_CLK_DIV(0));
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clrsetbits_le32(&ccm->cscmr1, CCM_REG_CTRL_MASK,
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CCM_CSCMR1_ESDHC1_CLK_SEL(3) |
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CCM_CSCMR1_NFC_CLK_SEL(0));
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clrsetbits_le32(&ccm->cscdr1, CCM_REG_CTRL_MASK,
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CCM_CSCDR1_RMII_CLK_EN);
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clrsetbits_le32(&ccm->cscdr2, CCM_REG_CTRL_MASK,
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CCM_CSCDR2_ESDHC1_EN | CCM_CSCDR2_ESDHC1_CLK_DIV(0) |
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CCM_CSCDR2_NFC_EN);
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clrsetbits_le32(&ccm->cscdr3, CCM_REG_CTRL_MASK,
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CCM_CSCDR3_NFC_PRE_DIV(5));
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clrsetbits_le32(&ccm->cscmr2, CCM_REG_CTRL_MASK,
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CCM_CSCMR2_RMII_CLK_SEL(2));
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}
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static void mscm_init(void)
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{
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struct mscm_ir *mscmir = (struct mscm_ir *)MSCM_IR_BASE_ADDR;
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int i;
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for (i = 0; i < MSCM_IRSPRC_NUM; i++)
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writew(MSCM_IRSPRC_CP0_EN, &mscmir->irsprc[i]);
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}
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int board_phy_config(struct phy_device *phydev)
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{
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if (phydev->drv->config)
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phydev->drv->config(phydev);
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return 0;
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}
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int board_early_init_f(void)
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{
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clock_init();
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mscm_init();
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setup_iomux_uart();
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setup_iomux_enet();
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setup_iomux_i2c();
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#ifdef CONFIG_NAND_VF610_NFC
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setup_iomux_nfc();
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#endif
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return 0;
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}
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#ifdef CONFIG_BOARD_LATE_INIT
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int board_late_init(void)
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{
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struct src *src = (struct src *)SRC_BASE_ADDR;
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/* Default memory arguments */
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if (!getenv("memargs")) {
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switch (gd->ram_size) {
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case 0x08000000:
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/* 128 MB */
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setenv("memargs", "mem=128M");
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break;
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case 0x10000000:
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/* 256 MB */
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setenv("memargs", "mem=256M");
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break;
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default:
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printf("Failed detecting RAM size.\n");
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}
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}
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if (((src->sbmr2 & SRC_SBMR2_BMOD_MASK) >> SRC_SBMR2_BMOD_SHIFT)
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== SRC_SBMR2_BMOD_SERIAL) {
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printf("Serial Downloader recovery mode, disable autoboot\n");
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setenv("bootdelay", "-1");
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}
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return 0;
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}
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#endif /* CONFIG_BOARD_LATE_INIT */
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int board_init(void)
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{
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struct scsc_reg *scsc = (struct scsc_reg *)SCSC_BASE_ADDR;
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/* address of boot parameters */
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gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
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/*
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* Enable external 32K Oscillator
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*
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* The internal clock experiences significant drift
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* so we must use the external oscillator in order
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* to maintain correct time in the hwclock
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*/
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setbits_le32(&scsc->sosc_ctr, SCSC_SOSC_CTR_SOSC_EN);
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return 0;
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}
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int checkboard(void)
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{
|
||||
if (is_colibri_vf61())
|
||||
puts("Board: Colibri VF61\n");
|
||||
else
|
||||
puts("Board: Colibri VF50\n");
|
||||
|
||||
return 0;
|
||||
}
|
||||
17
board/toradex/colibri_vf/imximage.cfg
Normal file
17
board/toradex/colibri_vf/imximage.cfg
Normal file
@@ -0,0 +1,17 @@
|
||||
/*
|
||||
* Copyright 2014 Toradex, Inc.
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*
|
||||
* Refer docs/README.imxmage for more details about how-to configure
|
||||
* and create imximage boot image
|
||||
*
|
||||
* The syntax is taken as close as possible with the kwbimage
|
||||
*/
|
||||
#include <asm/imx-common/imximage.cfg>
|
||||
|
||||
/* image version */
|
||||
IMAGE_VERSION 2
|
||||
|
||||
/* Boot Offset 0x400, valid for both SD and NAND boot */
|
||||
BOOT_OFFSET FLASH_OFFSET_STANDARD
|
||||
Reference in New Issue
Block a user