85xx: Fix how we map DDR memory

Previously we only allowed power-of-two memory sizes and didnt
handle >2G of memory.  Now we will map up to CONFIG_MAX_MEM_MAPPED
and should properly handle any size that we can make in the TLBs
we have available to us

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>

include/asm-ppc/config.h

@@ -22,7 +22,7 @@
 #define _ASM_CONFIG_H_
 
 #ifndef CONFIG_MAX_MEM_MAPPED
-#if defined(CONFIG_4xx)
+#if defined(CONFIG_4xx) || defined(CONFIG_E500)
 #define CONFIG_MAX_MEM_MAPPED	((phys_size_t)2 << 30)
 #else
 #define CONFIG_MAX_MEM_MAPPED	(256 << 20)

include/asm-ppc/processor.h

@@ -451,6 +451,8 @@
 #define   L2CSR0_L2LO		0x00000020	/* L2 Cache Lock Overflow */
 #define SPRN_L2CSR1	0x3fa	/* L2 Data Cache Control and Status Register 1 */
 
+#define SPRN_TLB0CFG	0x2B0	/* TLB 0 Config Register */
+#define SPRN_TLB1CFG	0x2B1	/* TLB 1 Config Register */
 #define SPRN_MMUCSR0	0x3f4	/* MMU control and status register 0 */
 #define SPRN_MAS0	0x270	/* MMU Assist Register 0 */
 #define SPRN_MAS1	0x271	/* MMU Assist Register 1 */

include/configs/MPC8572DS.h

@@ -103,6 +103,7 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy);
 
 /* DDR Setup */
 #define CONFIG_SYS_DDR_TLB_START 9
+#define CONFIG_VERY_BIG_RAM
 #define CONFIG_FSL_DDR2
 #undef CONFIG_FSL_DDR_INTERACTIVE
 #define CONFIG_SPD_EEPROM		/* Use SPD EEPROM for DDR setup */