Dave Liu 22c9de064a fsl-ddr: change the default burst mode for DDR3 ...

For 64B cacheline SoC, set the fixed 8-beat burst len,
for 32B cacheline SoC, set the On-The-Fly as default.

Signed-off-by: Dave Liu <daveliu@freescale.com>

2010-04-07 00:08:06 -05:00

..

ddr

fsl-ddr: change the default burst mode for DDR3

2010-04-07 00:08:06 -05:00

cpu.c

ppc/p4080: Add various p4080 related defines (and p4040)

2009-09-24 12:05:28 -05:00

fdt.c

ppc/85xx/86xx: Device tree fixup for number of cores

2009-09-08 09:10:08 -05:00

Makefile

ppc/85xx/86xx: Device tree fixup for number of cores

2009-09-08 09:10:08 -05:00

pci_cfg.c

ppc/8xxx: Remove is_fsl_pci_agent

2010-01-05 13:49:07 -06:00