York Sun f5b6fb7c1b powerpc/mpc8xxx: Fix DDR3 timing_cfg_1 and sdram_mode registers ...

The write recovery time of both registers should match. Since mode register
doesn't support cycles of 9,11,13,15, we should use next higher number for
both registers.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>

2011-03-05 10:13:50 -06:00

..

arm

ARM: Update mach-types

2011-02-21 08:30:55 +01:00

avr32

Switch from archive libraries to partial linking

2010-11-17 21:02:18 +01:00

blackfin

Divides variable of linker flags to LDFLAGS-u-boot and LDFLAGS

2011-01-25 22:22:30 +01:00

i386

sc520: Release CAR and enable caching

2011-02-12 15:12:12 +11:00

m68k

Replace "FLASH" strings with "Flash" or "flash"

2011-01-19 00:02:37 +01:00

microblaze

microblaze: Fix msr handling in interrupt_handler

2011-02-15 15:13:24 +01:00

mips

Switch from archive libraries to partial linking

2010-11-17 21:02:18 +01:00

nios2

nios2: add gpio_is_valid

2011-02-08 08:29:53 -05:00

powerpc

powerpc/mpc8xxx: Fix DDR3 timing_cfg_1 and sdram_mode registers

2011-03-05 10:13:50 -06:00

sh

sh: add support for sh7757lcr board

2011-02-02 16:38:41 +09:00

sparc

Replace "FLASH" strings with "Flash" or "flash"

2011-01-19 00:02:37 +01:00

.gitignore

update include/asm/ gitignore after move

2010-05-07 00:17:30 +02:00