Files
u-boot-tk1-som/arch
Stefan Agner da91cfed54 ARM: non-sec: flush code cacheline aligned
Flush operations need to be cacheline aligned to take effect, make
sure to flush always complete cachelines. This avoids messages such
as:
CACHE: Misaligned operation at range [00900000, 009004d9]

Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
Tested-by: Fabio Estevam <fabio.estevam@nxp.com>
2016-08-12 09:22:15 -04:00
..
2016-05-27 15:39:52 -04:00
2016-08-09 09:25:36 +02:00
2016-03-22 12:16:16 -04:00