Files
u-boot-tk1-som/arch
Siva Durga Prasad Paladugu f60c6fbbc6 ARM: zynq: slcr: Dont modify the reserved bits
Set only the 0-3 bits of the FPGA_RST_CTRL register
as other bits should not be set to 1.

Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Reviewed-by: Nathan Rossi <nathan.rossi@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2015-01-26 08:55:57 +01:00
..
2015-01-09 23:59:54 +03:00
2014-12-18 17:26:08 -07:00