This patch is added to update incorrect ddr and timer register offset. Signed-off-by: Chandan Nath <chandan.nath@ti.com> Signed-off-by: Tom Rini <trini@ti.com>
This patch is added to update incorrect ddr and timer register offset. Signed-off-by: Chandan Nath <chandan.nath@ti.com> Signed-off-by: Tom Rini <trini@ti.com>