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@@ -21,6 +21,7 @@
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#include "board.h"
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#include <power/pmic.h>
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#include <power/tps65218.h>
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#include <power/tps62362.h>
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#include <miiphy.h>
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#include <cpsw.h>
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@@ -138,6 +139,10 @@ const struct dpll_params epos_evm_dpll_ddr[NUM_CRYSTAL_FREQ] = {
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const struct dpll_params gp_evm_dpll_ddr = {
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50, 2, 1, -1, 2, -1, -1};
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static const struct dpll_params idk_dpll_ddr = {
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400, 23, 1, -1, 2, -1, -1
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};
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const struct ctrl_ioregs ioregs_lpddr2 = {
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.cm0ioctl = LPDDR2_ADDRCTRL_IOCTRL_VALUE,
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.cm1ioctl = LPDDR2_ADDRCTRL_WD0_IOCTRL_VALUE,
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@@ -282,6 +287,32 @@ static const struct emif_regs ddr3_sk_emif_regs_400Mhz = {
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.emif_cos_config = 0x000FFFFF
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};
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static const struct emif_regs ddr3_idk_emif_regs_400Mhz = {
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.sdram_config = 0x61a11b32,
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.sdram_config2 = 0x00000000,
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.ref_ctrl = 0x00000c30,
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.sdram_tim1 = 0xeaaad4db,
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.sdram_tim2 = 0x266b7fda,
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.sdram_tim3 = 0x107f8678,
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.read_idle_ctrl = 0x00050000,
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.zq_config = 0x50074be4,
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.temp_alert_config = 0x00000000,
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.emif_ddr_phy_ctlr_1 = 0x00008009,
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.emif_ddr_ext_phy_ctrl_1 = 0x08020080,
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.emif_ddr_ext_phy_ctrl_2 = 0x00000040,
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.emif_ddr_ext_phy_ctrl_3 = 0x0000003e,
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.emif_ddr_ext_phy_ctrl_4 = 0x00000051,
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.emif_ddr_ext_phy_ctrl_5 = 0x00000051,
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.emif_rd_wr_lvl_rmp_win = 0x00000000,
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.emif_rd_wr_lvl_rmp_ctl = 0x00000000,
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.emif_rd_wr_lvl_ctl = 0x00000000,
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.emif_rd_wr_exec_thresh = 0x00000405,
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.emif_prio_class_serv_map = 0x00000000,
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.emif_connect_id_serv_1_map = 0x00000000,
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.emif_connect_id_serv_2_map = 0x00000000,
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.emif_cos_config = 0x00ffffff
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};
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/*
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* get_sys_clk_index : returns the index of the sys_clk read from
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* ctrl status register. This value is either
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@@ -309,6 +340,8 @@ const struct dpll_params *get_dpll_ddr_params(void)
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return &epos_evm_dpll_ddr[ind];
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else if (board_is_gpevm() || board_is_sk())
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return &gp_evm_dpll_ddr;
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else if (board_is_idk())
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return &idk_dpll_ddr;
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printf(" Board '%s' not supported\n", am43xx_board_name);
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return NULL;
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@@ -364,24 +397,14 @@ const struct dpll_params *get_dpll_per_params(void)
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return &dpll_per[ind];
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}
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void scale_vcores(void)
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void scale_vcores_generic(u32 m)
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{
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const struct dpll_params *mpu_params;
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int mpu_vdd;
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struct am43xx_board_id header;
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enable_i2c0_pin_mux();
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i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE);
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if (read_eeprom(&header) < 0)
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puts("Could not get board ID.\n");
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/* Get the frequency */
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mpu_params = get_dpll_mpu_params();
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if (i2c_probe(TPS65218_CHIP_PM))
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return;
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switch (mpu_params->m) {
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switch (m) {
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case 1000:
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mpu_vdd = TPS65218_DCDC_VOLT_SEL_1330MV;
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break;
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@@ -405,17 +428,71 @@ void scale_vcores(void)
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/* Set DCDC1 (CORE) voltage to 1.1V */
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if (tps65218_voltage_update(TPS65218_DCDC1,
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TPS65218_DCDC_VOLT_SEL_1100MV)) {
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puts("tps65218_voltage_update failure\n");
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printf("%s failure\n", __func__);
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return;
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}
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/* Set DCDC2 (MPU) voltage */
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if (tps65218_voltage_update(TPS65218_DCDC2, mpu_vdd)) {
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puts("tps65218_voltage_update failure\n");
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printf("%s failure\n", __func__);
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return;
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}
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}
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void scale_vcores_idk(u32 m)
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{
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int mpu_vdd;
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if (i2c_probe(TPS62362_I2C_ADDR))
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return;
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switch (m) {
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case 1000:
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mpu_vdd = TPS62362_DCDC_VOLT_SEL_1330MV;
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break;
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case 800:
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mpu_vdd = TPS62362_DCDC_VOLT_SEL_1260MV;
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break;
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case 720:
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mpu_vdd = TPS62362_DCDC_VOLT_SEL_1200MV;
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break;
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case 600:
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mpu_vdd = TPS62362_DCDC_VOLT_SEL_1100MV;
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break;
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case 300:
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mpu_vdd = TPS62362_DCDC_VOLT_SEL_1330MV;
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break;
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default:
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puts("Unknown MPU clock, not scaling\n");
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return;
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}
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/* Set VDD_MPU voltage */
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if (tps62362_voltage_update(TPS62362_SET3, mpu_vdd)) {
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printf("%s failure\n", __func__);
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return;
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}
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}
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void scale_vcores(void)
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{
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const struct dpll_params *mpu_params;
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struct am43xx_board_id header;
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enable_i2c0_pin_mux();
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i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE);
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if (read_eeprom(&header) < 0)
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puts("Could not get board ID.\n");
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/* Get the frequency */
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mpu_params = get_dpll_mpu_params();
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if (board_is_idk())
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scale_vcores_idk(mpu_params->m);
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else
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scale_vcores_generic(mpu_params->m);
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}
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void set_uart_mux_conf(void)
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{
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enable_uart0_pin_mux();
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@@ -465,6 +542,9 @@ void sdram_init(void)
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} else if (board_is_sk()) {
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config_ddr(400, &ioregs_ddr3, NULL, NULL,
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&ddr3_sk_emif_regs_400Mhz, 0);
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} else if (board_is_idk()) {
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config_ddr(400, &ioregs_ddr3, NULL, NULL,
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&ddr3_idk_emif_regs_400Mhz, 0);
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}
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}
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#endif
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@@ -474,10 +554,17 @@ int power_init_board(void)
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{
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struct pmic *p;
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power_tps65218_init(I2C_PMIC);
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p = pmic_get("TPS65218_PMIC");
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if (p && !pmic_probe(p))
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puts("PMIC: TPS65218\n");
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if (board_is_idk()) {
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power_tps62362_init(I2C_PMIC);
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p = pmic_get("TPS62362");
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if (p && !pmic_probe(p))
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puts("PMIC: TPS62362\n");
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} else {
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power_tps65218_init(I2C_PMIC);
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p = pmic_get("TPS65218_PMIC");
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if (p && !pmic_probe(p))
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puts("PMIC: TPS65218\n");
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}
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return 0;
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}
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@@ -634,6 +721,10 @@ int board_eth_init(bd_t *bis)
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cpsw_slaves[0].phy_if = PHY_INTERFACE_MODE_RGMII;
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cpsw_slaves[0].phy_addr = 4;
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cpsw_slaves[1].phy_addr = 5;
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} else if (board_is_idk()) {
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writel(RGMII_MODE_ENABLE, &cdev->miisel);
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cpsw_slaves[0].phy_if = PHY_INTERFACE_MODE_RGMII;
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cpsw_slaves[0].phy_addr = 0;
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} else {
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writel(RGMII_MODE_ENABLE, &cdev->miisel);
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cpsw_slaves[0].phy_if = PHY_INTERFACE_MODE_RGMII;
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