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sunxi: dram: Remove broken impedance and ODT configuration code

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We can safely remove it, because none of the currently supported
boards uses these features.

The existing implementation had multiple problems:
   - unnecessary code duplication between sun4i/sun5i/sun7i
   - ZQ calibration was never initiated explicitly, and could be
     only triggered by setting the highest bit in the 'zq' parameter
     in the 'dram_para' struct (this was never actually done for
     any of the known Allwinner devices).
   - even if the ZQ calibration could be started, no attempts were
     made to wait for its completion, or checking whether the
     default automatically initiated ZQ calibration is still
     in progress
   - ODT was only ever enabled on sun4i, but not on sun5i/sun7i

Additionally, SDR_IOCR was set to 0x00cc0000 only on sun4i. There
are some hints in the Rockchip Linux kernel sources, indicating
that these bits are related to the automatic I/O power down
feature, which is poorly understood on sunxi hardware at the
moment. Avoiding to set these bits on sun4i too does not seem to
have any measurable/visible impact.

The impedance and ODT configuration code will be re-introdeced in
one of the next comits.

Signed-off-by: Siarhei Siamashka <siarhei.siamashka@gmail.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
This commit is contained in:
Siarhei Siamashka
2014-08-03 05:32:43 +03:00
committed by Hans de Goede
parent f8e88b6837
commit 7e40e1926a
1 changed files with 0 additions and 27 deletions
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27
arch/arm/cpu/armv7/sunxi/dram.c
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@@ -492,20 +492,9 @@ unsigned long dramc_init(struct dram_para *para)
writel(reg_val, &dram->dcr);
#ifdef CONFIG_SUN7I
setbits_le32(&dram->zqcr1, (0x1 << 24) | (0x1 << 1));
if (para->tpr4 & 0x2)
clrsetbits_le32(&dram->zqcr1, (0x1 << 24), (0x1 << 1));
dramc_clock_output_en(1);
#endif
#if (defined(CONFIG_SUN5I) || defined(CONFIG_SUN7I))
/* set odt impendance divide ratio */
reg_val = ((para->zq) >> 8) & 0xfffff;
reg_val |= ((para->zq) & 0xff) << 20;
reg_val |= (para->zq) & 0xf0000000;
writel(reg_val, &dram->zqcr0);
#endif
mctl_set_cke_delay();
#ifdef CONFIG_SUN7I
@@ -521,22 +510,6 @@ unsigned long dramc_init(struct dram_para *para)
mctl_enable_dllx(para->tpr3);
#ifdef CONFIG_SUN4I
/* set odt impedance divide ratio */
reg_val = ((para->zq) >> 8) & 0xfffff;
reg_val |= ((para->zq) & 0xff) << 20;
reg_val |= (para->zq) & 0xf0000000;
writel(reg_val, &dram->zqcr0);
#endif
#ifdef CONFIG_SUN4I
/* set I/O configure register */
reg_val = 0x00cc0000;
reg_val |= (para->odt_en) & 0x3;
reg_val |= ((para->odt_en) & 0x3) << 30;
writel(reg_val, &dram->iocr);
#endif
/* set refresh period */
dramc_set_autorefresh_cycle(para->clock, para->type - 2, density);