Stephen George 49e946cb6a board/t4240qds, b4860qds: LAW/TLB for DCSR set to size 32M ...

Debug trace buffers are memory mapped in DCSR space beyond 4M.

Signed-off-by: Stephen George <stephen.george@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>

2013-05-24 16:54:12 -05:00

12 KiB

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