9e6866d3b6
Move this driver over to use driver model. This involves rearranging the code somewhat. The effect is that everything is run from the probe() method. Boards which use this are fixed up, but only seaboard is tested. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Anatolij Gustschin <agust@denx.de> Signed-off-by: Tom Warren <twarren@nvidia.com>
52 lines
1.4 KiB
C
52 lines
1.4 KiB
C
/*
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* (C) Copyright 2010
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* NVIDIA Corporation <www.nvidia.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef __ASM_ARCH_TEGRA_DISPLAY_H
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#define __ASM_ARCH_TEGRA_DISPLAY_H
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#include <asm/arch-tegra/dc.h>
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#include <fdtdec.h>
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#include <asm/gpio.h>
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/* This holds information about a window which can be displayed */
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struct disp_ctl_win {
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enum win_color_depth_id fmt; /* Color depth/format */
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unsigned bpp; /* Bits per pixel */
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phys_addr_t phys_addr; /* Physical address in memory */
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unsigned x; /* Horizontal address offset (bytes) */
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unsigned y; /* Veritical address offset (bytes) */
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unsigned w; /* Width of source window */
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unsigned h; /* Height of source window */
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unsigned stride; /* Number of bytes per line */
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unsigned out_x; /* Left edge of output window (col) */
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unsigned out_y; /* Top edge of output window (row) */
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unsigned out_w; /* Width of output window in pixels */
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unsigned out_h; /* Height of output window in pixels */
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};
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#define FDT_LCD_TIMINGS 4
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enum {
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FDT_LCD_TIMING_REF_TO_SYNC,
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FDT_LCD_TIMING_SYNC_WIDTH,
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FDT_LCD_TIMING_BACK_PORCH,
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FDT_LCD_TIMING_FRONT_PORCH,
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FDT_LCD_TIMING_COUNT,
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};
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enum lcd_cache_t {
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FDT_LCD_CACHE_OFF = 0,
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FDT_LCD_CACHE_WRITE_THROUGH = 1 << 0,
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FDT_LCD_CACHE_WRITE_BACK = 1 << 1,
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FDT_LCD_CACHE_FLUSH = 1 << 2,
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FDT_LCD_CACHE_WRITE_BACK_FLUSH = FDT_LCD_CACHE_WRITE_BACK |
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FDT_LCD_CACHE_FLUSH,
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};
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#endif /*__ASM_ARCH_TEGRA_DISPLAY_H*/
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